IP Verification Engineer
Bengaluru, Karnataka, IndiaApply Now!
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits. SiFive is looking for verification engineers who are passionate about verifying industry-leading CPU and interconnect IP to help drive the tidal wave of adoption of RISC-V as the architecture of choice for SoC designs across a broad variety of vertical applications. We build and maintain multiple CPU family lines, TileLink interconnects and other uncore/infrastructure IP, and are seeking motivated individuals to join us to improve/evolve our existing IP, as well as develop new IPs. We have multiple positions open at various levels. Join us and surf the RISC-V wave with SiFive! Responsibilities:
- Hands on system Verilog/UVM development work for modern IPs including high performance Interconnects and system fabric IPs like IOMMU, Interrupt controller
- Creating a verification environment, testbenches, stimulus and coverage collateral.
- Working with the IP design team closely on test and debug strategy
- Sign off IP deliverable with defined quality metrics in terms of test pass rates, coverage goals.
- 2-10 (or more) years of experience in DV preferably in Interconnect or System Fabric IP verification.
- Proficiency in System Verilog and UVM methodology.
- Very good object oriented programming skills.
- Experience with RTL simulators and debugging methodology
- Any Bus interface knowledge like AMBA or PCIE. TileLink knowledge will be a big plus
- Any scripting knowledge, preferably python
- Integration experience with third party VIPs like interface bus VIPs
- SoC/CPU micro-arch knowledge with Interconnect knowledge as an added advantage
- Attention to detail and with great debugging and problem solving skills
- Ability to work well with others and a belief that engineering is a team sport.
- BS/MS degree in EE, CE, CS or a related technical discipline, or equivalent experience.