Junior Formal Verification Engineer
Austin, Texas, United StatesApply Now!
We at SiFive are looking for a Junior Formal Verification Engineer to join our growing team working on implementing a novel application of formal verification methodologies to parameterizable CPU IP generators. SiFive is looking for someone with outstanding knowledge and skills in formal verification who will build a formal environment to be used specifically with SiFive’s functional programming-based hardware design suite. Location: The ideal candidate for this position can work out of one of our US offices, preferably Austin, TX or Santa Clara, CA. Responsibilities:
- Assisting in the application of formal methodologies to parameterizable high-performance RISC-V CPU IP generators.
- Creating a reusable formal verification methodology library to be used in SiFive’s novel hardware design flow.
- Building a compiler-based hardware design suite that would automatically generate the appropriate test bench when given a parameterized instance of a chip design.
- Establishing through formal mathematical modeling or proofs the fidelity of given CPU IP blocks.
- Ensuring that CPU designs will meet given targets for power, performance, and area, by applying formal methods.
- Recent experience (work or school) in formal verification and related tools (model checking, property verification, JasperGold, Hector DPV, and others) and methodologies.
- Knowledge of CPU or GPU architectures (floating point, load-store, branch prediction, out-of-order execution) and cache coherence protocols.
- Experience in functional verification, such as constrained random verification, test bench generation, etc.
- Fluency in hardware description languages such as Verilog, VHDL, or SystemVerilog.
- Knowledge of Register-Transfer Level circuitry (registers, combinatorial function blocks (e.g. adders and multiplexers), finite state machines.
- Knowledge of Traditional test bench environments - UVM, Verdi/DVE.
- Functional programming languages, such as Scala, Chisel, Haskell, etc.