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About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits. This person will be responsible for the performance characterization and performance diagnostic analysis of applications running on FPGA-accelerated performance models of RISC-V cores. The candidate will need expertise in FPGA development workflows, the use of scripting languages to automate those workflows (Python preferred) as well as experience with bringing FPGA designs up and debugging them when things go wrong. Strong ability to navigate complex RTL system-level designs (in Verilog/VHDL or preferably Chisel), and a working knowledge of micro-architectures will help a candidate stand out. Responsibilities
- Using industry-leading FPGA platforms (AWS EC2 F1, Xilinx Alveo U250, Mentor Primo), the successful candidate will build, maintain and deploy FireSim models of next-generation RISC-V microarchitectures, use those models to run complex benchmarking workloads, analyze the resulting performance data, and debug performance outliers.
- Masters degree in Electrical Engineering, Computer Engineering or Computer Science (preferred), or bachelor’s degree with 2+ years of industry experience
- Closure of high-utilization designs with multiple clock domains in FPGA or ASIC (synthesis, place&route, timing) workflows
- Bringup and debug of FPGA systems, including use of Integrated Logic Analyzers and waveform debug
- Use of Python to automate tested workflows in a distributed computing environment
- Domain knowledge competency in computer micro-architectures
- Fluent in use of Python for development and testing of workflow automation
- Xilinx Vitis and/or Vivado FPGA development workflows (or comparable, including ASIC flows).
- RTL HDL familiarity sufficient to read and comprehend complex system-level designs (experience with Chisel and/or Scala is a plus)
- Mentor Primo FPGA prototyping platform (or comparable).
- Cloud infrastructure (AWS and/or Azure are a plus)
- Experience in Linux system administration
- C++ familiarity
- Python distributed workflows using Fabric
- Familiar with git or other source code control system
- Familiar with VSCode or other IDE for Python/C++/Scala development
- Strong ethic for automated testing of developed software