Physical Flow Integration Engineer
Hsinchu, TaiwanApply Now!
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit www.sifive.com. As a Physical Flow Integration Engineer, you will be joining a small team to architect, build and maintain physical design flows that work with SiFive’s generated RTL code. You will work closely with logic design, physical design and other teams to bring SiFive’s processor IP to market, as well as developing industry-leading automation to support SoC designs in a variety of vertical markets. This is the perfect opportunity for a tool-focused software engineer looking to expand their horizons and become more directly involved in developing innovative products in silicon. Summary Are you a person who likes to think wild with ideas to solve things? Are you passionate about finding the path to be smarter and more innovative? Are you the one who hunger for freedom and run after no boundaries? We have great opportunities for you. We are a Platform Execution Team, a group of people who are delivering an automation solution to get the complex job done, to save extra time with manual efforts. Here, you will work closely with design and implementation teams on the state-of-the-art RISC-V designs, wide coverage ranging from RTL code generation all the way down to Physical Design, you can learn or run things better from various aspects. Responsibilities
- Automate flow steps in various EDA tools to improve productivity.
- Perform PPA analysis on a series of the modern processors.
- Integrate the state-of-the-art process nodes and tool features into existing flow for enhancement.
- Develop an in-house QoR analytical system from initial planning to implementation stages.
- Construct and maintain a well-defined database to handle the complex dataset systematically.
- Design a deployment of a web-based dashboard to visualize the results of experiment, and drive it to be company standard flow.
- Cross collaboration with diverse teams worldwide.
- BS, MS or PhD in Computer Science, Electrical Engineering, or related technical fields.
- Familiarity with ASIC logic/physical design flow.
- Solid basic knowledge of shaping the software architecture and platform.
- Proficient in programming, such as Python, TCL, Shell, Makefile.
- Good communication skills, and interact across organizational boundaries.
- Hunger for success and willing for challenges.
- 3-5 years working experience in VLSI industry or software development experience.
- Experience in HTML, CSS, web development skills.
- Experience in version control system(Git).
- Experience in HDL (Verilog, VHDL, SystemVerilog)
- Experience in logic, physical, low-power design, PPA analysis of ASIC design.
- Experience in using EDA tools on VLSI, such as DC, Genus, ICC, Innovus, PT/PTPX, PowerArtist.