Senior CPU Design Verification Engineer - Test Program Generator
Hsinchu, TaiwanApply Now!
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit www.sifive.com. Stay current with the latest SiFive updates via Facebook, LinkedIn, Twitter, and YouTube. As a Design Verification Engineer, you will work with CPU designers, compiler team, performance team, and system verification team to generate the test cases automatically to fit those teams' verification requirements in different perspectives. Your responsibilities will target establishing a random instruction test generator that produces self-checking direct test cases. Responsibilities:
- Design, develop, documentation and deploy random instruction generators and support multiple projects.
- Support execution of the generator and flows in the RTL design process.
- Integrate and ramp upon an existing instruction-level verification flow.
- Bachelor's, or Master's in Computer Science, Electrical Engineering, or a similar discipline.
- Familiarity or academic experience with hardware design and verification.
- Experience with basic CPU micro-architecture (and related technologies and algorithms), as well as functional verification and simulation tools.
- Experience with software project architecture/design and python/C++11 above programming.
- Basic understanding of Verilog, System-Verilog RTL, UVM, and constraint random verification.