Senior RTL Design Engineer, LSU/MMU
San Mateo, California, United StatesApply Now!
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits. As a Senior RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open-source RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance. Responsibilities:
- Architecting, designing and implementing new features, performance improvements, and ISA extensions in RISC-V CPU core generators with a focus on the load/store unit and L1 data cache memory subsystem.
- Microarchitecture development and specification. Ensuring that knowledge is shared via great documentation and participation in a culture of collaborative design.
- Performing initial sandbox verification, and working with the design verification team to create and execute thorough verification test plans.
- Work with the physical implementation team to implement and optimize physical design to meet frequency, area, power goals.
- Collaborating with the performance modelling team for performance exploration and optimization to meet performance goals.
- 7+ years of recent industry experience in high-performance, energy-efficient CPU designs:
- Expertise in CPU processor designs in one or more of the following areas: load-store unit; L1 data cache, cache coherence, memory consistency, and Memory Management Unit (MMU).
- Background of successful CPU development from architecture through tape-out and vector units; load-store unit; cache and memory subsystems.
- Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.
- Knowledge of at least one object-oriented and/or functional programming language.
- Attention to detail and a focus on high-quality design.
- Ability to work well with others and a belief that engineering is a team sport.