Posted Apr 26, 2022

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  Senior CPU Design Verification Engineer - Golden Model and Instruction Checker
  SiFive
  Hsinchu, Taiwan, Hsinchu, Taiwan
  Verilog RTL

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  Senior CPU Design Verification Engineer - Test Program Generator
  SiFive
  Hsinchu, Taiwan, Hsinchu, Taiwan
  Verilog RTL

Posted Feb 25, 2022

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  RTL Design Engineer - RISC-V CPU
  SiFive
  Hsinchu, Taiwan, Hsinchu, Taiwan
  VHDL Verilog System Verilog RTL

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  Senior RTL Design Engineer - RISC-V CPU
  SiFive
  Hsinchu, Taiwan, Hsinchu, Taiwan
  VHDL Verilog System Verilog RTL