Posted Jun 15, 2022

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  SOC Physical Design STA/Timing Engineer (Silicon Engineering)
  SpaceX
  Mountain View, CA, United States, Mountain View, CA, United States
  Verilog System Verilog ASIC

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  Sr. Physical Design Engineer, Top Level (Silicon Engineering)
  SpaceX
  Mountain View, CA, United States, Mountain View, CA, United States
  Verilog System Verilog ASIC

Posted May 28, 2022

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  Principal DFT Design Engineer (Silicon Engineering)
  SpaceX
  Mountain View, CA, United States, Mountain View, CA, United States
  Verilog SystemVerilog ASIC RTL

Posted May 27, 2022

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  Principal SOC Physical Design Engineer (Silicon Engineering)
  SpaceX
  Mountain View, CA, United States, Mountain View, CA, United States
  Verilog System Verilog ASIC

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  Sr. SOC Synthesis & Front-End STA Engineer (Silicon Engineering)
  SpaceX
  Mountain View, CA, United States, Mountain View, CA, United States
  Verilog SystemVerilog ASIC RTL

Posted May 24, 2022

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  Design Verification Engineer (Silicon Engineering)
  SpaceX
  Mountain View, CA, United States, Mountain View, CA, United States
  FPGA ASIC RTL

Posted May 18, 2022

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  ASIC/FPGA Design Engineer - DSP (Starlink)
  SpaceX
  Mountain View, CA, United States, Mountain View, CA, United States
  VHDL Verilog SystemVerilog FPGA ASIC RTL

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  Sr. SOC DFT Design Engineer (Starlink)
  SpaceX
  Mountain View, CA, United States, Mountain View, CA, United States
  Verilog SystemVerilog ASIC RTL