Design Verification Engineer
Apple
Cupertino
, California
, United States
Verilog
SystemVerilog
RTL
Verification
$150,400 – $225,300/year
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Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Review the design specifications, extracting attributes, and reviewing the test plan with verification, design and cross functional teams. Generate coverage databases and collaborating with design team to close the coverage. Develop regression scripts and running regressions on Apple‘s regression infrastructure. File tickets to track RTL bugs, providing designers with the waveform of the bug and the reproduction command. Develop test bench environment(s), directed and random/constrained tests to completely verify the design features. Develop functional coverage metrics to meet the verification goals. Develop reusable and scalable testbenches which can be easily integrated in higher level environments. Plan and develop checkers to identify design bugs. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.
PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field.
Experience and/or education must include:
Using SystemVerilog for constrained random test development
Using C for reference model and checker development.
Utilizing Perl, Python, or shell scripting for regression automation.
Applying Digital Electronics concepts to understand the design under test.
Utilizing simulators and waveform viewers, including VCS or Verdi, for running and debugging simulations.
Utilizing CPU architecture knowledge for verifying CPU based designs.
Using knowledge of Verilog RTL design constructs for debugging designs.
Using MATLAB to create models used in verification.
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