today

Engineer Electrical Level 3/4 - Command and Data Handling - Dulles

Northrop Grumman Dulles, Virginia

FPGA Digital Design

17h

Sr Principal Systems Engineer – Verification Product Owner (26-384)

Northrop Grumman Springs, Colorado

Verification

17h

FPGA Architecture Engineer

Lattice Semiconductor San Jose, California

VHDL Verilog

17h

Junior Digital Design Engineer

NXP Semiconductors Nijmegen, Gelderland

VHDL Verilog

17h

Internship Student Analog Mixed Signal verification F/M

NXP Semiconductors Catania, Sicily

Verification

17h

Senior DFT Methodology Engineer

NVIDIA Santa Clara, California

RTL STA

17h

Technical Program Manager – DFX Productization

NVIDIA Santa Clara, California

ASIC SOC

17h

Senior DFT Methodology Engineer

NVIDIA Santa Clara, California

RTL STA

17h

Senior ASIC Verification Engineer

NVIDIA Multiple locations

SystemVerilog ASIC

17h

Emulation Engineer / Emulation Platform Engineer -Senior

Qualcomm Austin, Texas

ASIC RTL

18h

DFT-Staff Engineer

Qualcomm Austin, Texas

ASIC RTL

18h

DFT- Sr. Engineer

Qualcomm San Diego, California

ASIC RTL

18h

SoC Clock & Power Management Validation Lead, Staff (AI Accelerator Platform)

Qualcomm San Diego, California

Verilog System Verilog

18h

System Validation Lead, Staff (AI Accelerator Platform)

Qualcomm San Diego, California

VHDL Verilog

18h

DDR Validation Lead, Staff (AI Accelerator Platform)

Qualcomm San Diego, California

FPGA ASIC

18h

Physical Design Engineer

Qualcomm Tijuana, Baja California

ASIC RTL

18h

ISP Design Engineer, up to Staff

Qualcomm Taipei, Taipei

Verilog System Verilog

18h

Senior ASIC Verification Engineer

Qualcomm Markham, Ontario

VHDL Verilog

18h

SoC Static Timing Analysis (STA) Engineer, HBM

Micron Multiple locations

RTL STA

18h

Senior Design Verification Engineer

Silicon Labs Austin, Texas

SystemVerilog UVM

18h

CPU-SoC Structural Design Engineer

Intel Penang, Malaysia

STA Static Timing

18h

SoC Analog & Mixed-Signal Design Engineer

Intel Hillsboro, Oregon

SOC Verification

18h

Senior Digital Verification Engineer

Allegro MicroSystems Prague, Praha, Hlavní město

VHDL Verilog

18h

ASIC Engineering Intern

HPE Juniper Networks Durham, North Carolina

ASIC Verification

18h

Research Scientist - Loop Engineering and AI Infrastructure

SK hynix memory solutions America Inc. San Jose, California

FPGA ASIC

18h

Staff Embedded Engineer, EW

Anduril Costa Mesa, California

VHDL Verilog

19h

Senior FPGA Verification Engineer

Anduril Boulder, Colorado

VHDL Verilog

19h

Senior FPGA Verification Engineer

Anduril Goleta, California

VHDL Verilog

19h

Senior FPGA Verification Engineer

Anduril Waltham, Massachusetts

VHDL Verilog

19h

Senior Firmware Engineer, Space

Anduril Boulder, Colorado

VHDL Verilog

19h

Senior Firmware Engineer

Anduril Waltham, Massachusetts

VHDL Verilog

19h

Principal Verification Engineer

CesiumAstro Aliso Viejo, California

SystemVerilog ASIC

19h

yesterday

Design Verification Engineer

Broadcom San Jose, California

Verilog System Verilog

1d

IC Verification Engineer

Broadcom IND-Bangalore Electronic City - S1

Verilog System Verilog

1d

Senior QA/DV Program Manager

Axiado Hyderabad, Telangana

FPGA ASIC

1d

Library Characterization Engineer

Microchip Technology Rousset, Provence-Alpes-Côte-d’Azur

STA Place and Route

1d

Principle Engineer - CAD (Physical Verification)

Microchip Technology Chandler, Arizona

FPGA ASIC

1d

INTERN_NVE Design Eng

Micron Avezzano, Abruzzo

VHDL Verilog

1d

INTERN_NVE Design Eng

Micron Avezzano, Abruzzo

VHDL Verilog

1d

Design Engineer

Micron Avezzano, Abruzzo

Verilog RTL

1d

Senior DFT Engineer - Post Silicon

NVIDIA Multiple locations

DFT

1d

Senior Software Engineer - SOC Platforms

NVIDIA Santa Clara, California

SOC

1d

Microarchitecture and Design Engineer - AI SoC

Intel Multiple locations

SystemVerilog RTL

1d

SOC RTL Design Engineer

Intel Multiple locations

SystemVerilog RTL

1d

SOC Design Verification Engineer

Intel Multiple locations

RTL Register Transfer

1d

IP Design - Staff engineer

Qualcomm Chennai, Tamil Nadu

Verilog RTL

1d

GPU Design Verification Engineer

Qualcomm Boxborough, Massachusetts

VHDL Verilog

1d

Pre-Silicon Validation Engineer

Qualcomm San Diego, California

SystemVerilog FPGA

1d

CPU Server Physical Design Engineer, Santa Clara

Qualcomm Santa Clara, California

VHDL Verilog

1d

FY27 Intern - Digital Design Intern - Hod Hasharon

Qualcomm Hod HaSharon, Central District

Verilog System Verilog

1d