yesterday

Principal Engineer

Microchip Technology Bangalore, India

DFT Design for Test

21h

Engineer I-Design

Microchip Technology Allentown, Pennsylvania

Verilog SystemVerilog

21h

Associate Staff Physical Design Engineer

Silicon Labs Hyderabad, Telangana

Verilog SystemVerilog

21h

Digital Circuit Design Engineer - DRAM Design

Micron Boise, Idaho

RTL STA

21h

Principal PCIe Application Engineer

Micron San Jose, California

FPGA ASIC

21h

Software Engineer III – Radiation Effects Tooling

Blue Origin Greater Seattle Area

VHDL Verilog

22h

Senior EDA Tools Hardware Engineer

Intel Multiple locations

Digital Design STA

22h

E-core CPU Design Manager

Intel Penang, Malaysia

RTL Static Timing

22h

E-core CPU Physical Design Engineer

Intel Penang, Malaysia

RTL Place and Route

22h

E-core CPU Physical Design Engineer

Intel Penang, Malaysia

RTL Place and Route

22h

E-core CPU Physical Design Engineer

Intel Penang, Malaysia

RTL Place and Route

22h

E-core CPU Physical Design Engineer

Intel Penang, Malaysia

RTL Place and Route

22h

E-core CPU Physical Design Engineer

Intel Penang, Malaysia

RTL Place and Route

22h

E-core Senior CPU Physical Design Engineer

Intel Penang, Malaysia

RTL Place and Route

22h

E-core Senior CPU Physical Design Engineer

Intel Penang, Malaysia

RTL Place and Route

22h

E-core Senior CPU Physical Design Engineer

Intel Penang, Malaysia

RTL Place and Route

22h

E-core Senior CPU Physical Design Engineer

Intel Penang, Malaysia

RTL Place and Route

22h

AI-Driven Physical Design Engineering (PhD Intern)

Intel Multiple locations

RTL Digital Design

22h

Pre-Silicon Verification Engineer

Intel Multiple locations

Verilog System Verilog

22h

Senior Distribution Sales Manager

Lattice Semiconductor Taipei, Taipei

FPGA ASIC

22h

Design Verification Engineer 2

Lattice Semiconductor Pune, Maharashtra

Verilog System Verilog

22h

Engineer, Digital Design Engineering

Analog Devices Bangalore, India

Verilog SystemVerilog

22h

Senior DFT engineer

Broadcom Singapore, Central Singapore

Verilog ASIC

22h

DFT Engineer

Qualcomm San Diego, California

ASIC RTL

22h

IC/FPGA Design Verification Engineer, Sr Staff

Qualcomm Ottawa, Ontario

SystemVerilog FPGA

22h

SoC Sr Validation Engineer - Power Management

Qualcomm Bangalore, India

FPGA ASIC

22h

ASIC/FPGA Design Verification Engineer, Senior

Qualcomm Ottawa, Ontario

Verilog SystemVerilog

22h

Chip Lead

Silicon Labs Austin, Texas

Verilog System Verilog

22h

ASIC Engineer Intern

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

22h

ASIC Clocks Verification Engineer - New College Grad 2026

NVIDIA Santa Clara, California

SystemVerilog ASIC

22h

Lead Physical Design Engineer

NXP Semiconductors Pune, Maharashtra

RTL STA

23h

Sr. ASIC Design Engineer (Silicon Engineering)

SpaceX Palo Alto, California

Verilog System Verilog

23h

ASIC Design Engineer (Silicon Engineering)

SpaceX Palo Alto, California

VHDL Verilog

23h

Sr Staff Analog IC Design Engineer

Ambiq Micro, Inc. Austin, Texas

RTL SOC

23h

Oct. 9, 2026

Embedded AI Tools Engineer

Analog Devices Wilmington, Massachusetts

FPGA Synthesis

1d

Staff Engineer, Digital Design Engineering

Analog Devices Multiple locations

RTL Digital Design

1d

CPU Physical Design Engineer

Intel Austin, Texas

RTL Logic Design

1d

Microarchitecture and Design Engineer - AI SoC

Intel Bangalore, India

SystemVerilog RTL

1d

Pre-Silicon SoC Validation - Technical Lead

Intel Bangalore, India

SystemVerilog RTL

1d

Pre-Si Power Performance Val & Opt Engineer (Contract)

Intel Multiple locations

FPGA RTL

1d

CPU Physical Design Engineer

Intel Austin, Texas

RTL Static Timing

1d

Senior Principal Backend Engineer (CORTEX - Autonomous SOC)

Palo Alto Networks Tel Aviv, Tel Aviv District

SOC

1d

Senior Manager-Design Engineering

Microchip Technology Multiple locations

VHDL Verilog

1d

Senior Physical Design Engineer

NVIDIA Multiple locations

STA Place and Route

1d

Senior Software Engineer, DOCA Verification

NVIDIA Multiple locations

Verification

1d

Senior Circuit Design Engineer

NVIDIA Santa Clara, California

RTL STA

1d

Senior Product Engineer, Mixed Signal SOC — TeraWave

Blue Origin Multiple locations

ASIC DFT

1d

Senior Product Engineer, Modem SOC — TeraWave

Blue Origin Central Texas

ASIC DFT

1d

Principal L1 PHY & Modem Implementation Engineer

Blue Origin Kraków, Lesser Poland Voivodeship

FPGA ASIC

1d

ASICS Engineer-Senior to Staff

Qualcomm San Diego, California

ASIC RTL

1d