today

Physical Design Engineer, Staff

Qualcomm Hyderabad, Telangana

FPGA ASIC

18h

SOC Design Verification Engineer

Qualcomm San Diego, California

ASIC RTL

18h

Summer 2027 - Electrical Engineering Internship, FPGA

CesiumAstro El Segundo, California

VHDL Verilog

19h

yesterday

Engineer Electrical Level 3/4 - Command and Data Handling - Dulles

Northrop Grumman Dulles, Virginia

FPGA Digital Design

1d

Sr Principal Systems Engineer – Verification Product Owner (26-384)

Northrop Grumman Springs, Colorado

Verification

1d

FPGA Architecture Engineer

Lattice Semiconductor San Jose, California

VHDL Verilog

1d

Junior Digital Design Engineer

NXP Semiconductors Nijmegen, Gelderland

VHDL Verilog

1d

Internship Student Analog Mixed Signal verification F/M

NXP Semiconductors Catania, Sicily

Verification

1d

Senior DFT Methodology Engineer

NVIDIA Santa Clara, California

RTL STA

1d

Technical Program Manager – DFX Productization

NVIDIA Santa Clara, California

ASIC SOC

1d

Senior DFT Methodology Engineer

NVIDIA Santa Clara, California

RTL STA

1d

Senior ASIC Verification Engineer

NVIDIA Multiple locations

SystemVerilog ASIC

1d

Emulation Engineer / Emulation Platform Engineer -Senior

Qualcomm Austin, Texas

ASIC RTL

1d

DFT-Staff Engineer

Qualcomm Austin, Texas

ASIC RTL

1d

DFT- Sr. Engineer

Qualcomm San Diego, California

ASIC RTL

1d

SoC Clock & Power Management Validation Lead, Staff (AI Accelerator Platform)

Qualcomm San Diego, California

Verilog System Verilog

1d

System Validation Lead, Staff (AI Accelerator Platform)

Qualcomm San Diego, California

VHDL Verilog

1d

DDR Validation Lead, Staff (AI Accelerator Platform)

Qualcomm San Diego, California

FPGA ASIC

1d

Physical Design Engineer

Qualcomm Tijuana, Baja California

ASIC RTL

1d

ISP Design Engineer, up to Staff

Qualcomm Taipei, Taipei

Verilog System Verilog

1d

Senior ASIC Verification Engineer

Qualcomm Markham, Ontario

VHDL Verilog

1d

SoC Static Timing Analysis (STA) Engineer, HBM

Micron Multiple locations

RTL STA

1d

Senior Design Verification Engineer

Silicon Labs Austin, Texas

SystemVerilog UVM

1d

CPU-SoC Structural Design Engineer

Intel Penang, Malaysia

STA Static Timing

1d

SoC Analog & Mixed-Signal Design Engineer

Intel Hillsboro, Oregon

SOC Verification

1d

Senior Digital Verification Engineer

Allegro MicroSystems Prague, Praha, Hlavní město

VHDL Verilog

1d

ASIC Engineering Intern

HPE Juniper Networks Durham, North Carolina

ASIC Verification

1d

Research Scientist - Loop Engineering and AI Infrastructure

SK hynix memory solutions America Inc. San Jose, California

FPGA ASIC

1d

Staff Embedded Engineer, EW

Anduril Costa Mesa, California

VHDL Verilog

1d

Senior FPGA Verification Engineer

Anduril Boulder, Colorado

VHDL Verilog

1d

Senior FPGA Verification Engineer

Anduril Goleta, California

VHDL Verilog

1d

Senior FPGA Verification Engineer

Anduril Waltham, Massachusetts

VHDL Verilog

1d

Senior Firmware Engineer, Space

Anduril Boulder, Colorado

VHDL Verilog

1d

Senior Firmware Engineer

Anduril Waltham, Massachusetts

VHDL Verilog

1d

Principal Verification Engineer

CesiumAstro Aliso Viejo, California

SystemVerilog ASIC

1d

Oct. 2, 2026

Design Verification Engineer

Broadcom San Jose, California

Verilog System Verilog

2d

IC Verification Engineer

Broadcom IND-Bangalore Electronic City - S1

Verilog System Verilog

2d

Senior QA/DV Program Manager

Axiado Hyderabad, Telangana

FPGA ASIC

2d

Library Characterization Engineer

Microchip Technology Rousset, Provence-Alpes-Côte-d’Azur

STA Place and Route

2d

Principle Engineer - CAD (Physical Verification)

Microchip Technology Chandler, Arizona

FPGA ASIC

2d

Design Engineer

Micron Avezzano, Abruzzo

Verilog RTL

2d

Senior DFT Engineer - Post Silicon

NVIDIA Multiple locations

DFT

2d

Senior Software Engineer - SOC Platforms

NVIDIA Santa Clara, California

SOC

2d

Microarchitecture and Design Engineer - AI SoC

Intel Multiple locations

SystemVerilog RTL

2d

SOC RTL Design Engineer

Intel Multiple locations

SystemVerilog RTL

2d

SOC Design Verification Engineer

Intel Multiple locations

RTL Register Transfer

2d

IP Design - Staff engineer

Qualcomm Chennai, Tamil Nadu

Verilog RTL

2d

GPU Design Verification Engineer

Qualcomm Boxborough, Massachusetts

VHDL Verilog

2d

Pre-Silicon Validation Engineer

Qualcomm San Diego, California

SystemVerilog FPGA

2d

CPU Server Physical Design Engineer, Santa Clara

Qualcomm Santa Clara, California

VHDL Verilog

2d