today

Principal / Sr. Principal PCB Layout Design Engineer

Northrop Grumman Woodland Hills, California

DFT Design for Test

16h

RTL Design Engineering Student

Intel Israel, Petah-Tikva

SystemVerilog RTL

16h

Silicon Design - Flows and Methodology Intern

Intel Guadalajara, Jalisco

Verilog System Verilog

16h

RTL Design Engineer

Intel Multiple locations

VHDL Verilog

16h

Senior DFT Logic Design Engineer

Intel Multiple locations

ASIC RTL

16h

Digital Verification Engineer - MCU

NXP Semiconductors Catania, Sicily

SystemVerilog UVM

16h

Mixed Signal Design Engineer

NXP Semiconductors Tianjin, Tianjin

SOC IP Design

16h

Architect - GPU Performance

NVIDIA Bengaluru, Karnataka

Verilog System Verilog

16h

Senior Architect, GPU and SoC Modeling

NVIDIA Santa Clara, California

SOC

16h

Senior ASIC Design Engineer

NVIDIA Santa Clara, California

Verilog System Verilog

16h

Manager, Project Management - Chip Design

NVIDIA Tel Aviv, Tel Aviv District

Verilog SystemVerilog

16h

NVTHERM SoC Verification Intern, Tegra - 2027

NVIDIA Shanghai, Shanghai

Verilog SystemVerilog

16h

Design Engineer

Silicon Labs Oslo

Digital Design Synthesis

16h

Principal Field Application Engineer

SiFive Shanghai, Shanghai

FPGA RTL

16h

Senior ASIC Diagnostic Engineer

HPE Juniper Networks Bloomington, Minnesota

ASIC

16h

Senior Principal ASIC Design Engineer

HPE Juniper Networks Roseville, California

Verilog SystemVerilog

16h

SoC Audio Architect, Platform Architecture

Apple Multiple Locations

SOC IP Design

17h

SoC Audio Engineer, Platform Architecture

Apple Multiple Locations

SOC IP Design

17h

Infra Systems Physical Architect

Qualcomm San Diego, California

ASIC Place and Route

17h

DRAM PHY Designer, up to Staff

Qualcomm Hsinchu City, Taiwan

ASIC RTL

17h

SMMU Senior Lead Design Verification Engineer

Qualcomm Bangalore, India

Verilog System Verilog

17h

RTL Design (Director)

Qualcomm Hyderabad, Telangana

Digital Design Synthesis

17h

Design Verification Engineer, Senior Staff

Qualcomm Toronto, Ontario

SystemVerilog ASIC

17h

SoC Design Verification Engineer (Up to Principal Level)

Qualcomm Ho Chi Minh City, Hồ Chí Minh

SystemVerilog FPGA

17h

SoC RTL Design Engineer (Up to Principal Level)

Qualcomm Ho Chi Minh City, Hồ Chí Minh

Verilog SystemVerilog

17h

CPU Physical Design Engineer

Qualcomm Austin, Texas

VHDL Verilog

17h

SOC Power Architect

Qualcomm San Diego, California

ASIC SOC

17h

Camera VI Engineer

Qualcomm Tijuana, Baja California

Verilog SystemVerilog

17h

Electrical Engineering Intern, Summer 2027

BAE Systems Westminster, Colorado

FPGA Digital Design

17h

Senior Principal FPGA Design Engineer

BAE Systems Totowa, New Jersey

VHDL Verilog

17h

Senior Robotics Verification & Validation (V&V) Engineering Manager

Johnson & Johnson Boston, Massachusetts

Verification

17h

Test and Verification Engineer

Philips Shenzhen

Verification

17h

DFT Manager

Broadcom IND-Bangalore Electronic City - S1

ASIC DFT

17h

Digital Design Verification Engineer

Broadcom Multiple locations

UVM SOC

17h

Senior Embedded Engineer, EW

Anduril Costa Mesa, California

VHDL Verilog

17h

Electrical Manufacturing Engineer

Anduril Atlanta, Georgia

FPGA Digital Design

17h

Electro-Optic Systems Architect

Lightmatter Multiple locations

RTL Digital Design

17h

Senior FPGA Engineer

Astranis San Francisco, California

Verilog SystemVerilog

18h

yesterday

Embedded Firmware Design Engineer (m/f/d)

NXP Semiconductors Gratkorn

Digital Design HDL

1d

GSoC Design Verification Engineer

Qualcomm San Diego, California

Verilog System Verilog

1d

GPU Design Implementation Engineer

Qualcomm San Diego, California

ASIC RTL

1d

ASIC Design Verification Engineer

Qualcomm Santa Clara, California

ASIC RTL

1d

DSP Core Design Engineer, Principal (U.S. Potential Relocation)

Qualcomm Hsinchu City, Taiwan

ASIC RTL

1d

ASIC Design Verification Engineer (Santa Clara, CA)

Qualcomm Santa Clara, California

Verilog SystemVerilog

1d

SoC Power Design Engineer (Engineer - Staff Eng)

Qualcomm San Diego, California

VHDL Verilog

1d

Power Modelling Engineer, Staff

Qualcomm Bangalore, India

ASIC RTL

1d

Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm San Diego, California

ASIC RTL

1d

SoC Performance Architect (Server CPU)

Qualcomm Multiple locations

SOC

1d

Staff / Senior Staff Engineer - ASIC / NoC SoC deployment architect - Qualcomm - Guyancourt, France

Qualcomm Guyancourt, Île-de-France

ASIC RTL

1d

Physical Design Engineer

Qualcomm San Diego, California

ASIC RTL

1d