today

ASICS Design Verification Engineer-Senior

Qualcomm San Diego, California

VHDL Verilog

18h

ASICS Engineer

Qualcomm San Diego, California

ASIC RTL

18h

SoC Power Design Engineer

Qualcomm San Diego, California

ASIC RTL

18h

NoC Interconnect Design Engineer and Architect

Qualcomm Santa Clara, California

ASIC RTL

18h

Principal SOC Architect, AI Accelerators (Multiple Locations

Qualcomm Multiple Locations

ASIC SOC

18h

(Sr) Staff SOC Architect - AI Accelerators (Multiple Locations)

Qualcomm Multiple Locations

ASIC SOC

18h

Senior Digital Design Engineer GPU Hardware Design - Athens

Qualcomm Maroúsi, Attica Region

Verilog SystemVerilog

18h

Staff Digital Design Engineer GPU Hardware - Athens

Qualcomm Maroúsi, Attica Region

Verilog SystemVerilog

18h

Senior Software CAD Engineer - Cork, IRL

Qualcomm Cork, Munster

Verilog SystemVerilog

18h

Staff / Senior Staff Engineer - ASIC / NoC SoC deployment architect - Qualcomm - Guyancourt, France

Qualcomm Guyancourt, Île-de-France

ASIC RTL

18h

Senior ASIC Design Verification Engineer - Slingshot

HPE Juniper Networks Bloomington, Minnesota

SystemVerilog FPGA

18h

FPGA Design Engineer

HPE Juniper Networks Spring, Texas

Verilog FPGA

18h

Senior Principal Embedded Software Architect

Analog Devices Multiple locations

Verilog SystemVerilog

19h

Engineer, FPGA Design

Analog Devices Cluj-Napoca, Cluj County

VHDL Verilog

19h

Sr FPGA Design Engineer (NetSec)

Palo Alto Networks Headquarters, California

Verilog SystemVerilog

19h

Engineer II - Hardware

Microchip Technology MA - Beverly Tozer

VHDL Verilog

19h

Engineer II - Verification

Microchip Technology Chennai, Tamil Nadu

Verilog System Verilog

19h

Staff Engineer Electronics

Northrop Grumman Chandler, Arizona

VHDL FPGA

19h

Principal Design Engineer

Micron San Jose, California

RTL STA

19h

Principal Modem PHY IP Design Engineer - Terawave

Blue Origin Multiple locations

FPGA ASIC

19h

Senior Analog Mixed-Signal IC Design Engineer - TeraWave

Blue Origin Multiple locations

SystemVerilog Digital Design

19h

RF Systems FPGA Engineer II - Lunar Permanance

Blue Origin Greater Seattle Area

VHDL Verilog

19h

Principal Engineer, Physical Design

Marvell Hsinchu City

ASIC RTL

19h

Senior Staff Manager, Physical Design

Marvell Hsinchu City

ASIC RTL

19h

Senior Staff, Emulation Engineer

Marvell Bangalore, India

Verilog SystemVerilog

19h

IC Design Engineer

Broadcom Multiple locations

RTL STA

19h

IC Design Engineer

Broadcom Multiple locations

RTL STA

19h

IC Design Engineer

Broadcom Multiple locations

RTL STA

19h

RTL IC Design Engineer

Broadcom Multiple locations

Verilog SystemVerilog

19h

IC Design Engineer

Broadcom Fort Collins, Colorado

Verilog ASIC

19h

Senior Software Engineer, DOCA Verification

NVIDIA Multiple locations

Verification

19h

Physical Verification Engineer

NVIDIA Multiple locations

ASIC SOC

19h

Senior Physical Verification Engineer

NVIDIA Multiple locations

ASIC Verification

19h

Senior Verification Engineer – High Speed Coherent Interconnect Hub

NVIDIA Santa Clara, California

SystemVerilog FPGA

19h

Senior FPGA Prototyping Engineer - Hardware

NVIDIA Santa Clara, California

Verilog System Verilog

19h

SoC Power Management Validation Engineer

Intel Penang, Malaysia

SOC

19h

Logic Design Engineer

Intel Penang, Malaysia

Verilog SystemVerilog

19h

Staff Logic Design Engineer

Intel Penang, Malaysia

Verilog System Verilog

19h

DFT Design Engineering Intern

Intel Penang, Malaysia

Verilog System Verilog

19h

SoC Design Verification Engineer

Intel Santa Clara, California

RTL UVM

19h

Design Verification Graduate Intern 2027

Intel Multiple locations

VHDL Verilog

19h

GPU Physical Design Engineer

Intel San Jose, California

ASIC Static Timing

19h

Senior Principal Electrical Engineer II (Sign On Available)

BAE Systems Hudson, New Hampshire

VHDL FPGA

20h

Principal Electrical Engineer

BAE Systems Hudson, New Hampshire

VHDL Verilog

20h

Senior Principal Electrical Engineer - FPGA VHDL Design (Sign on Bonus)

BAE Systems Merrimack, New Hampshire

VHDL Verilog

20h

Staff RTL Design Engineer - Cache Subsystem

SiFive Hsinchu, Hsinchu

VHDL Verilog

20h

Mixed-Signal Verification Engineer

Apple Multiple Locations

Verilog System Verilog

20h

Mixed-Signal Verification Engineer

Apple Multiple Locations

Verilog System Verilog

20h

Design Verification Engineer

Apple Multiple Locations

Verilog SystemVerilog

20h

Design Verification Engineer

Apple Multiple Locations

Verilog SystemVerilog

20h