today

Backend Physical Design Engineer

Broadcom IND-Bangalore Electronic City - S1

Digital Design STA

16h

Principal FPGA Micro-Architect

Lattice Semiconductor San Jose, California

Verilog SystemVerilog

16h

VLSI ASIC Logic Design Engineer

HPE Juniper Networks Multiple locations

Verilog System Verilog

16h

FPGA Designer - TeraWave RF and Optical Systems Firmware

Blue Origin Greater Seattle Area

VHDL Verilog

16h

Principal FPGA Designer – TeraWave

Blue Origin Greater Seattle Area

VHDL Verilog

16h

Sr ASIC Design Engineer - TeraWave

Blue Origin Multiple locations

VHDL Verilog

16h

Principal Engineer, HIG-HBM Product System Engineering (Media Health Manufacturing)

Micron Singapore, Central Singapore

Verilog DFT

16h

Engineer, HIG-HBM Product System & Engineering (Media Health Manufacturing)

Micron Singapore, Central Singapore

Verilog DFT

16h

SoC Power Thermal Performance Val and Opt Engineer (Temporary Position)

Intel Guadalajara, Jalisco

17h

GPU Validation Engineer

Intel Toronto, Ontario

Verilog System Verilog

17h

Principal Electrical Engineer

BAE Systems Dallas, Texas

VHDL Verilog

17h

Senior Engineer II - Layout

Microchip Technology San Jose, California

ASIC SOC

17h

Senior SoC Architect, RAS

NVIDIA Multiple locations

RTL Design for Test

17h

Power Engineer

Apple Cupertino, California

RTL Logic Design

17h

FE Engineer

Apple San Diego, California

Verilog SystemVerilog

17h

Power Engineer

Apple Cupertino, California

ASIC RTL

17h

FE Engineer

Apple Cupertino, California

Verilog RTL

17h

Power Engineer

Apple Cupertino, California

ASIC RTL

17h

FE Engineering

Apple Cupertino, California

Verilog System Verilog

17h

CPU Implementation Engineer

Apple Cupertino, California

Verilog RTL

17h

Firmware Validation Engineer

Apple San Francisco, California

RTL SOC

17h

Firmware Validation Engineer

Apple San Francisco, California

RTL SOC

17h

Manager Digital Engineering 2

Northrop Grumman Multiple locations

FPGA ASIC

17h

Staff Systems Engineer - Verification Lead - Futures

Northrop Grumman Multiple locations

Verification

17h

• GPU Design Implementation Engineer (Synthesis) - Cork, Ireland

Qualcomm Cork, Munster

ASIC SOC

17h

FY27 Intern - HW/FW Architecture for Post-Quantum Cryptography - 6 months, Sophia

Qualcomm Bainbridge, Alpes-de-Haute-Provence, France

VHDL Verilog

17h

FY27 Intern - CHERI-Based Prototype for Root of Trust Security - 6 months, Sophia

Qualcomm Bainbridge, Alpes-de-Haute-Provence, France

Verilog System Verilog

17h

FY27 Intern - CPU Engineering Internship 2027 - 6 months, Cork

Qualcomm Cork, Munster

Verilog System Verilog

17h

Design Implementation Synthesis Engineer, Sr Lead

Qualcomm Bangalore, India

RTL Synthesis

17h

GPU Physical Design Engineer (Senior/Lead)

Qualcomm Bangalore, India

RTL STA

17h

DFT - Senior Engineer

Qualcomm Bangalore, India

ASIC RTL

17h

Sr Engineer - Peripheral Validation

Qualcomm Bangalore, India

ASIC RTL

17h

Technical Lead – LINT, CDC & RDC Verification

NXP Semiconductors Noida, Uttar Pradesh

RTL Synthesis

18h

Physical Design and Verification Engineer

Neuralink South San Francisco, California, United States

RTL STA

18h

Physical Design Engineer

Baya Systems Multiple locations

Verilog System Verilog

18h

Senior FPGA Engineer II

Rocket Lab Long Beach, California

VHDL FPGA

18h

yesterday

Physical Design Clocking Engineer

Intel Santa Clara, California

RTL Static Timing

1d

Pre-si Power and Performance System Validation Engineer

Intel Multiple locations

FPGA RTL

1d

Principal Engineer, SOC Performance Architecture

Intel Multiple locations

SOC Verification

1d

ASIC Principal Design Engineer

HPE Juniper Networks Heredia, Heredia Province

FPGA ASIC

1d

ASIC Design Engineer I

HPE Juniper Networks Heredia, Heredia Province

FPGA ASIC

1d

ASIC Design Engineer

HPE Juniper Networks Heredia, Heredia Province

FPGA ASIC

1d

Senior / Staff Verification Engineer - RF/TIA (Analog Mixed Signal)

Marvell Singapore, Central Singapore

Verilog Verification

1d

Engineering IP Program Manager, Principal

Marvell Bangalore, India

ASIC Design for Test

1d

Staff Engineer- DFT

Marvell Santa Clara, California

Verilog SystemVerilog

1d

Sr Staff Engineer-DFT

Marvell Santa Clara, California

ASIC STA

1d

Senior Principal Engineer-DFT

Marvell Santa Clara, California

ASIC Logic Design

1d

Avionics Hardware Engineer III

Blue Origin Denver, Colorado

FPGA DFT

1d

Avionics Hardware Engineer III

Blue Origin Denver, Colorado

FPGA DFT

1d

2027 Electrical Engineer - Digital Hardware Design - Dulles VA

Northrop Grumman Dulles, Virginia

VHDL Verilog

1d