today

Head - SoC Physical Design Manager

NXP Semiconductors Sophia-Antipolis (Valbonne); Gratkorn

RTL STA

24m

Sr ASIC Design Engineer

Blue Origin Kraków, Lesser Poland Voivodeship

VHDL Verilog

32m

Senior Verification Engineer

Blue Origin Kraków, Lesser Poland Voivodeship

SystemVerilog ASIC

32m

Principal Verification Engineer

Blue Origin Kraków, Lesser Poland Voivodeship

SystemVerilog ASIC

32m

Electrical Engineer - Multiple Levels

AeroVironment Multiple locations

FPGA Digital Design

44m

Staff Design Engineer

Lattice Semiconductor Pune, Maharashtra

FPGA ASIC

54m

Manager, Design Eng (Design Verification)

Lattice Semiconductor Penang, Malaysia

Verilog System Verilog

54m

Hardware Engineering Intern

HPE Juniper Networks Westford, Massachusetts

Verilog FPGA

1h

Senior ASIC Verification Engineer

HPE Juniper Networks Heredia, Heredia Province

FPGA ASIC

1h

Engineer II - Design

Microchip Technology Vietnam - Saigon

FPGA ASIC

1h

Engineer I-Verification

Microchip Technology Vietnam - Saigon

Verification

1h

Engineer I-Software

Microchip Technology Toronto, Ontario

FPGA Static Timing

1h

Technical Staff Engineer - Layout

Microchip Technology Allentown, Pennsylvania

Place and Route Synthesis

1h

DFT Lead Engineer

Broadcom San Jose, California

Verilog ASIC

1h

Peripherals Design Verification -Sr Engineer

Qualcomm Bangalore, India

Verilog System Verilog

1h

Peripherals Design Verification - Staff Engineer

Qualcomm Bangalore, India

Verilog System Verilog

1h

NOC Design Verification Sr Engineer

Qualcomm Noida, Uttar Pradesh

FPGA ASIC

1h

Verification Engineer

Intel Bangalore, India

SystemVerilog FPGA

1h

Senior DFT Design Engineer

Intel Multiple locations

RTL Register Transfer

1h

FPGA Design Lead

BAE Systems Multiple locations

VHDL Verilog

1h

Senior Digital Design Engineer

NVIDIA Multiple locations

ASIC RTL

1h

Senior Verification Engineer - CPU

NVIDIA Multiple locations

Verification

1h

Principal Engineer, SRAM Design

Micron Multiple locations

RTL SOC

2h

Sr/Staff/Principle/MTS Design Engineer

Micron Multiple locations

ASIC SOC

2h

FPGA Implementation Engineer (JR)

Cirrus Logic Austin, Texas

Verilog System Verilog

2h

yesterday

Test Engineer (ATE)

Broadcom San Jose, California

ASIC DFT

1d

Staff IC Verification Engineer

Broadcom Fort Collins, Colorado

VHDL Verilog

1d

ASIC Physical Design Engineer

Broadcom Singapore, Central Singapore

RTL Synthesis

1d

PCIe Design Engineer

Broadcom IND-Bangalore Electronic City - S1

ASIC RTL

1d

PCIe Design Engineer

Broadcom IND-Bangalore Electronic City - S1

ASIC RTL

1d

IC Design Engineer

Broadcom Singapore, Central Singapore

RTL Synthesis

1d

IC Design Engineer

Broadcom Singapore, Central Singapore

RTL Synthesis

1d

R&D Engineer IC Design

Broadcom IND-Bangalore Electronic City - S1

ASIC STA

1d

R&D Engineer IC Design

Broadcom IND-Bangalore Electronic City - S1

ASIC STA

1d

STAFF DFT Engineer

Broadcom IND-Bangalore Electronic City - S1

ASIC STA

1d

STAFF DFT Engineer

Broadcom IND-Bangalore Electronic City - S1

ASIC STA

1d

R&D Engineer IC Design

Broadcom IND-Bangalore Electronic City - S1

ASIC STA

1d

DFT Senior Engineer

Broadcom IND-Bangalore Electronic City - S1

ASIC STA

1d

DFT Senior Engineer

Broadcom IND-Bangalore Electronic City - S1

ASIC STA

1d

DFT Staff Engineer

Broadcom Pune, Maharashtra

ASIC STA

1d

DFT Senior Engineer

Broadcom Pune, Maharashtra

ASIC STA

1d

IC Design Engineer (DFT)

Broadcom Shanghai, Shanghai

ASIC RTL

1d

Senior DFT engineer

Broadcom Singapore, Central Singapore

Verilog ASIC

1d

Senior DFT engineer

Broadcom Singapore, Central Singapore

Verilog ASIC

1d

Senior DFT engineer

Broadcom Singapore, Central Singapore

Verilog ASIC

1d

Senior DFT engineer

Broadcom Singapore, Central Singapore

Verilog ASIC

1d

Senior DFT engineer

Broadcom Singapore, Central Singapore

Verilog ASIC

1d

IC Design Engineer

Broadcom Singapore, Central Singapore

RTL Synthesis

1d

IC Design Engineer

Broadcom Singapore, Central Singapore

ASIC RTL

1d

ASIC Physical Design Engineer

Broadcom Singapore, Central Singapore

RTL Synthesis

1d