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Physical Design Clocking Engineer

Intel Santa Clara, California

RTL Static Timing

Pre-si Power and Performance System Validation Engineer

Intel Multiple locations

FPGA RTL

Principal Engineer, SOC Performance Architecture

Intel Multiple locations

SOC Verification

ASIC Principal Design Engineer

HPE Juniper Networks Heredia, Heredia Province

FPGA ASIC

ASIC Design Engineer I

HPE Juniper Networks Heredia, Heredia Province

FPGA ASIC

ASIC Design Engineer

HPE Juniper Networks Heredia, Heredia Province

FPGA ASIC

Senior / Staff Verification Engineer - RF/TIA (Analog Mixed Signal)

Marvell Singapore, Central Singapore

Verilog Verification

Engineering IP Program Manager, Principal

Marvell Bangalore, India

ASIC Design for Test

Staff Engineer- DFT

Marvell Santa Clara, California

Verilog SystemVerilog

Sr Staff Engineer-DFT

Marvell Santa Clara, California

ASIC STA

Senior Principal Engineer-DFT

Marvell Santa Clara, California

ASIC Logic Design

Avionics Hardware Engineer III

Blue Origin Denver, Colorado

FPGA DFT

Avionics Hardware Engineer III

Blue Origin Denver, Colorado

FPGA DFT

2027 Electrical Engineer - Digital Hardware Design - Dulles VA

Northrop Grumman Dulles, Virginia

VHDL Verilog

Design Engineer II

Silicon Labs Austin, Texas

Verilog System Verilog

Digital Design Engineer, Coherent High Speed Interconnect - New College Graduate

NVIDIA Multiple locations

Verilog System Verilog

Staff DRAM RTL Design Engineer

Micron Hyderabad, Telangana

ASIC RTL

Principal Engineer, Design verification

Micron Hyderabad, Telangana

Verilog System Verilog

Senior Design Verification Engineer

Micron Minneapolis, Minnesota

SystemVerilog ASIC

ASIC Analog Design Engineer

Micron Minneapolis, Minnesota

ASIC Verification

Staff Engineer, ASIC Analog Design – AI/CAD

Micron Minneapolis, Minnesota

ASIC Verification

Senior ASIC Silicon Validation Engineer (NetSec)

Palo Alto Networks Headquarters, California

SystemVerilog ASIC

Principal Engineer - Digital Design

Microchip Technology Colorado Springs, Colorado

Senior Engineer II - AMS Verification

Microchip Technology Chennai, Tamil Nadu

Verilog SystemVerilog

Senior Engineer I - Verification

Microchip Technology Chennai, Tamil Nadu

SystemVerilog RTL

Engineer I - Design

Microchip Technology Hauppauge, New York

FPGA ASIC

Engineer I - Software

Microchip Technology San Jose, California

FPGA Static Timing

Senior Engineer - Modem System Validation

Qualcomm Bangalore, India

ASIC SOC

FY27 Intern - Display IP FPGA Emulation Intern - Canada (4 months)

Qualcomm Markham, Ontario

VHDL Verilog

FY27 Intern - FPGA Intern, Hod Hasharon, Israel

Qualcomm Hod HaSharon, Central District

Verilog SystemVerilog

Staff Digital Design Engineer

Qualcomm Bangalore, India

Verilog SystemVerilog

ASIC Validation Engineer

Qualcomm Bangalore, India

FPGA ASIC

FY27 Intern - CPU Engineering Internship 2027 - 6 months, Cork

Qualcomm Cork, Munster

Verilog System Verilog

Senior Principal Design Verification Engineer

NXP Semiconductors Bangalore, India

SystemVerilog UVM

Senior/Principal Analog IC Circuit Design Engineer

NXP Semiconductors Eindhoven, North Brabant

Verilog ASIC

Director of Firmware Engineering

Celero Communications, Inc. Ottawa, Ontario

SystemVerilog FPGA

10h

yesterday

Head - SoC Physical Design Manager

NXP Semiconductors Sophia-Antipolis (Valbonne); Gratkorn

RTL STA

Sr ASIC Design Engineer

Blue Origin Kraków, Lesser Poland Voivodeship

VHDL Verilog

Senior Verification Engineer

Blue Origin Kraków, Lesser Poland Voivodeship

SystemVerilog ASIC

Principal Verification Engineer

Blue Origin Kraków, Lesser Poland Voivodeship

SystemVerilog ASIC

Electrical Engineer - Multiple Levels

AeroVironment Multiple locations

FPGA Digital Design

Staff Design Engineer

Lattice Semiconductor Pune, Maharashtra

FPGA ASIC

Manager, Design Eng (Design Verification)

Lattice Semiconductor Penang, Malaysia

Verilog System Verilog

Hardware Engineering Intern

HPE Juniper Networks Westford, Massachusetts

Verilog FPGA

Senior ASIC Verification Engineer

HPE Juniper Networks Heredia, Heredia Province

FPGA ASIC

Engineer II - Design

Microchip Technology Vietnam - Saigon

FPGA ASIC

Engineer I-Verification

Microchip Technology Vietnam - Saigon

Verification

Engineer I-Software

Microchip Technology Toronto, Ontario

FPGA Static Timing

Technical Staff Engineer - Layout

Microchip Technology Allentown, Pennsylvania

Place and Route Synthesis

DFT Lead Engineer

Broadcom San Jose, California

Verilog ASIC

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