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Engineer II - FPGA Verification

BAE Systems Westminster, Colorado

VHDL Verilog

21h

Senior Principal FPGA Design Engineer

BAE Systems Austin, Texas

VHDL FPGA

21h

ASICS Design Verification Engineer- (Multiple Levels)

Qualcomm San Diego, California

SystemVerilog ASIC

21h

RFA Design Engineer, Senior

Qualcomm Bangalore, India

ASIC RTL

21h

NOC DV Staff Engineer

Qualcomm Bangalore, India

Verilog System Verilog

21h

DFT Engineer, Staff

Qualcomm Toronto, Ontario

VHDL Verilog

21h

Sr. Staff Hardware Design Engineer, SoC/SIP

Qualcomm Multiple locations

SOC

21h

Verification Engineer

Philips Shenyang, Liaoning

Verification

21h

Senior FPGA Verification Engineer

Anduril Boulder, Colorado

VHDL Verilog

21h

Senior FPGA Verification Engineer

Anduril Goleta, California

VHDL Verilog

21h

Senior FPGA Verification Engineer

Anduril Waltham, Massachusetts

VHDL Verilog

21h

Senior Firmware Engineer

Anduril Waltham, Massachusetts

VHDL Verilog

21h

Senior Embedded Engineer

Anduril Waltham, Massachusetts

VHDL Verilog

21h

FPGA Verification Engineer II

CesiumAstro Westminster, Colorado

VHDL Verilog

22h

Lead PCB Designer (Starshield)

SpaceX Hawthorne, California

FPGA Digital Design

22h

Software Engineering Manager

Baya Systems Bengaluru, Karnataka

SOC IP Design

22h

Senior Engineer, Design Verification

Samsung Semiconductor San Jose, California

Verilog System Verilog

22h

Embedded Software Designer - AI Knowledge and Data

Fidus Systems Kitchener, Ontario

FPGA ASIC

22h

Embedded Software Designer - AI Agents and Tooling

Fidus Systems Kitchener, Ontario

FPGA ASIC

22h

Nov. 13, 2026

R&D Engineer Physical Design

Broadcom San Jose, California

STA Static Timing

R&D Engineer Physical Design

Broadcom San Jose, California

ASIC RTL

R&D Engineer Physical Design

Broadcom San Jose, California

ASIC RTL

ASIC Design Engineer

Broadcom Multiple locations

ASIC Place and Route

ASIC Design Engineer

Broadcom Multiple locations

ASIC Place and Route

Principal Physical Design Engineer — ASIC Products Division (APD)

Broadcom San Jose, California

ASIC STA

Senior Microarchitecture and Design Engineer - AI SoC

Intel Bangalore, India

SystemVerilog RTL

Senior Formal Verification Engineer

Intel Bangalore, India

Verilog System Verilog

Principal Engineer - Validation (ASIC)

Microchip Technology Basking Ridge, New Jersey

ASIC

Senior ATE Hardware Engineer

Lattice Semiconductor Penang, Malaysia

FPGA DFT

Digital Hardware Engineer

BAE Systems Nashua, New Hampshire

FPGA Digital Design

Mixed Signal Design Engineer Intern

Analog Devices Bari, Apulia

Verilog SystemVerilog

Memory Design Engineer

Allegro MicroSystems Milan, Lombardy

Verilog SystemVerilog

Design Methodology – Staff DRAM Power Integrity Engineer

Micron Hyderabad, Telangana

RTL STA

ASIC Reliability Analysis (RA) Engineer

Micron Hyderabad, Telangana

ASIC Verification

SoC Physical Design Formal Verification Engineer, HBM

Micron Multiple locations

Verilog SystemVerilog

HBM Hardware Emulation Engineer

Micron Multiple locations

FPGA RTL

Senior Digital Design Engineer, HBM

Micron Richardson, Texas

Verilog SystemVerilog

Senior Digital Design Engineer, HBM

Micron Richardson, Texas

Verilog SystemVerilog

Staff Engineer, Embedded Sensor Systems & Physical AI

Qualcomm San Diego, California

FPGA ASIC

Sr Staff Engineer - Verification, CI/CD Infrastructure & Embedded Hardware (AISW)

Qualcomm Markham, Ontario

Verification

FPGA Engineer II

CesiumAstro Westminster, Colorado

VHDL Verilog