today

Principal/Sr. Principal Engineer Systems-20424

Northrop Grumman Roy, Utah

VHDL Verilog

18h

Sr. Principal Electrical Engineer (FPGA Design Engineer)

Northrop Grumman San Diego, California

FPGA UVM

18h

Staff FPGA Digital Engineer - 5

Northrop Grumman Chandler, Arizona

VHDL Verilog

18h

Principal Engineer, Design

Micron Tokyo, Tokyo

RTL STA

19h

Engineer - HIG HBM - PE Design Validation

Micron Singapore, Central Singapore

VHDL Verilog

19h

HBM SoC Physical Design Engineer

Micron Richardson, Texas

RTL STA

19h

Senior Engineer Design

Micron Hyderabad, Telangana

Verilog RTL

19h

Principal Design Engineer, HBM Architecture

Micron Richardson, Texas

RTL STA

19h

Sr/ Staff Design Engineer/Architect(Datapath), HBM

Micron Richardson, Texas

RTL STA

19h

Analog ASIC Design Intern (Summer 2027)

Draper Cambridge, Massachusetts

Verilog System Verilog

19h

Principal Engineer - Design for Test

Microchip Technology Bangalore, India

19h

Senior Engineer I-Design • FPGA Applications

Microchip Technology Hyderabad, Telangana

FPGA SOC

19h

Principal Senior Engineer - FPGA Design - $30K Sign On Bonus

BAE Systems Westminster, Colorado

VHDL Verilog

19h

Senior FPGA Design Engineer - $30K Sign On Bonus

BAE Systems Westminster, Colorado

VHDL Verilog

19h

Engineer II - FPGA Verification

BAE Systems Westminster, Colorado

VHDL Verilog

19h

Principal Electrical Engineer (Sign on Bonus)

BAE Systems Multiple locations

VHDL Verilog

19h

Electrical Engineering Internship Summer 2027

BAE Systems Wayne, New Jersey

VHDL Verilog

19h

Integration Design Engineer

Lattice Semiconductor Manila, Metro Manila

Verilog System Verilog

19h

FY27 Intern - Formal Verification Engineering Internship - 6 months, Cambridge

Qualcomm Cambridge, England

Verilog HDL

19h

SOC Verification and Methodology Engineer

Qualcomm San Diego, California

Verilog SystemVerilog

19h

GPU Design Verification Engineer, Senior

Qualcomm San Diego, California

VHDL Verilog

19h

FY27 Intern - Camera Design Engineering Internship - Canada (12 or 16 months)

Qualcomm Vancouver, British Columbia

Verilog System Verilog

19h

High-Speed Analog & Mixed-Signal PHY Design Engineer

Qualcomm San Diego, California

VHDL Verilog

19h

CPU Physical Design Engineer (Lead/Staff/Sr. Staff)

Qualcomm Bangalore, India

FPGA RTL

19h

ASIC RTL Design Engineer (Sr. Engr / Sr. Lead Engr)

Qualcomm Bangalore, India

Verilog ASIC

19h

NOC DV Engineer

Qualcomm Bangalore, India

Verilog System Verilog

19h

Design Verification (NPU) - Sr Lead Engineer

Qualcomm Bangalore, India

FPGA ASIC

19h

RTL Design (NPU) - Sr Lead

Qualcomm Bangalore, India

FPGA Verification

19h

FPGA Prototyping Engineer

Intel Penang, Malaysia

FPGA RTL

20h

FPGA Prototyping Engineer

Intel Penang, Malaysia

Verilog System Verilog

20h

Sr. MSIAM SOC Engineer (Unit 42)

Palo Alto Networks Charlotte, North Carolina

SOC

20h

Software Verification Engineer

NVIDIA Raanana, Israel

Verification

20h

Architecture Energy Modeling Engineer

NVIDIA Shanghai, Shanghai

Verilog ASIC

20h

Software Verification Engineer

NVIDIA Yokneam, Israel

Verification

20h

Senior CPU Power Architect

NVIDIA Santa Clara, California

ASIC RTL

20h

Senior Physical Design Methodology Engineer, PPA Improvement Technology Scaling

NVIDIA Multiple locations

Place and Route SOC

20h

Working Student (f/m/d) Digital Physical Design

NXP Semiconductors Dresden

VHDL SystemVerilog

20h

Technical Director - FE

NXP Semiconductors Noida, Uttar Pradesh

ASIC RTL

20h

Physical Design Lead

NXP Semiconductors Bangalore, India

ASIC RTL

20h

Staff Design Verification Engineer, AI Hardware

Tenstorrent Belgrade, Central Banat District

RTL UVM

20h

Senior Design Verification Engineer, AI Hardware

Tenstorrent Belgrade, Central Banat District

SystemVerilog RTL

20h

Principal FPGA Design Engineer

Terran Orbital Irvine, California

VHDL SystemVerilog

20h

Group Lead, Firmware & Software

HRL Laboratories Calabasas, California

VHDL Verilog

20h

yesterday

Senior VLSI ASIC Logic Design Engineer

HPE Juniper Networks Multiple locations

FPGA ASIC

1d

Senior VLSI ASIC Logic Design Engineer

HPE Juniper Networks Multiple locations

FPGA ASIC

1d

Senior DRAM RTL design engineer

Micron Hyderabad, Telangana

ASIC RTL

1d

PRINCIPAL ENGINEER, ASIC DESIGN

Micron Hyderabad, Telangana

Verilog System Verilog

1d

PRINCIPAL ENGINEER, ASIC DESIGN

Micron Hyderabad, Telangana

Verilog System Verilog

1d

PRINCIPAL ENGINEER, ASIC DESIGN

Micron Hyderabad, Telangana

Verilog System Verilog

1d

Senior Engineer, DPG LPDDR Verification

Micron Hyderabad, Telangana

Verilog System Verilog

1d