today

DFT Engineer / GPU Logic Design Engineer

Intel Bangalore, India

RTL Register Transfer

17h

Digital Verification Senior Manager

NXP Semiconductors Multiple locations

SystemVerilog UVM

17h

2027 Intern - STA agent developer Intern

NXP Semiconductors Tianjin, Tianjin

STA

17h

Senior Design Verification Engineer

Lattice Semiconductor Penang, Malaysia

SystemVerilog FPGA

17h

Senior Design Verification Engineer

Lattice Semiconductor Penang, Malaysia

SystemVerilog FPGA

17h

Staff Design Verification Engineer

Lattice Semiconductor Penang, Malaysia

SystemVerilog FPGA

17h

Design Verification Engineer

Lattice Semiconductor Penang, Malaysia

SystemVerilog FPGA

17h

Principal FPGA Digital Engineer - 3

Northrop Grumman Chandler, Arizona

VHDL Verilog

18h

FPGA Digital Engineer - 2

Northrop Grumman Chandler, Arizona

VHDL Verilog

18h

VLSI Engineer I -

HPE Juniper Networks Roseville, California

FPGA Logic Design

18h

CAD Engineer

NVIDIA Bengaluru, Karnataka

RTL UVM

18h

Senior Manager, Cryptographic Engineering

IonQ Geneva, Switzerland

FPGA RTL

19h

yesterday

Staff Engineer, Design Verification Engineering

Analog Devices Bangalore, India

FPGA ASIC

1d

Physical design Engineer

NXP Semiconductors Bangalore, India

RTL STA

1d

Oct. 17, 2026

Senior System Level Verification Engineer

Axiado Hyderabad, Telangana

FPGA ASIC

2d

Senior Engineer II - Backend Implementation

Microchip Technology Bangalore, India

Verilog STA

2d

Senior Engineer II - Backend Implementation

Microchip Technology Hyderabad, Telangana

Verilog FPGA

2d

Principal Engineer – Design Engineering

Microchip Technology Bangalore, India

VHDL Verilog

2d

Principal Engineer-Design (SoC Integration and RTL/IP)

Microchip Technology Chandler, Arizona

SystemVerilog FPGA

2d

Analog Mixed Signal Firmware Engineer

Apple Cupertino, California

Verilog SystemVerilog

2d

Wireless SoC Design Engineer

Apple Multiple Locations

Verilog ASIC

2d

Wireless SoC Design Engineer

Apple Multiple Locations

Verilog ASIC

2d

Wireless RTL Design Engineer

Apple Multiple Locations

RTL Logic Design

2d

Principal/Sr. Principal FPGA Design Engineer

Northrop Grumman Rolling Meadows, Illinois

FPGA Verification

2d

FPGA Digital Design Engineer Level 3 (AHT)

Northrop Grumman Northridge, California

VHDL Verilog

2d

Test Engineer (ATE)

Broadcom San Jose, California

ASIC DFT

2d

System Verification Engineer

NVIDIA Austin, Texas

FPGA ASIC

2d

Senior System Verification Engineer

NVIDIA Austin, Texas

Verilog FPGA

2d

Senior System Verification Engineer

NVIDIA Austin, Texas

Verilog FPGA

2d

Safety product development F/M

NXP Semiconductors Multiple locations

DFT SOC

2d

Digital IP Design - Senior Lead Engineer

NXP Semiconductors Noida, Uttar Pradesh

VHDL Verilog

2d

Safety product development F/M

NXP Semiconductors Noida, Uttar Pradesh

DFT SOC

2d

FPGA Systems Development Engineer

Analog Devices Copenhagen, Capital Region of Denmark

FPGA RTL

2d

Principal Electrical Engineer (Sign On Bonus Available)

BAE Systems Nashua, New Hampshire

VHDL FPGA

2d

Senior Principal Electrical Engineer (Sign On Available)

BAE Systems Nashua, New Hampshire

VHDL FPGA

2d

Principal Electrical Engineer (Sign On Bonus Available)

BAE Systems Nashua, New Hampshire

VHDL FPGA

2d

Senior Principal FPGA (VHDL) Design Engineer - Sign on Bonus Available

BAE Systems Nashua, New Hampshire

VHDL Verilog

2d

Senior Principal FPGA Design Engineer

BAE Systems Wayne, New Jersey

VHDL Verilog

2d

Sr. Verification Engineer

Blue Origin Longmont, Colorado

VHDL SystemVerilog

2d

Intern - Memory Design Engineer, HBM

Micron Richardson, Texas

VHDL Verilog

2d

Senior Design Verification Engineer

Micron San Jose, California

RTL Verification

2d

E-core CPU Full Chip Physical Design Engineer

Intel Penang, Malaysia

STA Synthesis

2d

E-core CPU Power Delivery Engineer

Intel Penang, Malaysia

RTL SOC

2d

Staff Logic Design Engineer

Intel Penang, Malaysia

Verilog System Verilog

2d

GPU Performance Verification Engineer

Intel Bangalore, India

RTL UVM

2d

Senior SOC Design Engineer

Intel Penang, Malaysia

RTL UVM

2d

GPU Design Verification Engineer

Intel Multiple locations

Verilog System Verilog

2d

GPU Design Verification Engineer

Intel Multiple locations

Verilog System Verilog

2d

SoC Logic Design Engineer

Intel San Jose, California

SystemVerilog RTL

2d

Lead SoC Performance Architect

Qualcomm Santa Clara, California

RTL SOC

2d