yesterday

R&D Engineer Physical Design

Broadcom San Jose, California

STA Static Timing

20h

R&D Engineer Physical Design

Broadcom San Jose, California

ASIC RTL

20h

R&D Engineer Physical Design

Broadcom San Jose, California

ASIC RTL

20h

ASIC Design Engineer

Broadcom Multiple locations

ASIC Place and Route

20h

ASIC Design Engineer

Broadcom Multiple locations

ASIC Place and Route

20h

Principal Physical Design Engineer — ASIC Products Division (APD)

Broadcom San Jose, California

ASIC STA

20h

Senior Microarchitecture and Design Engineer - AI SoC

Intel Bangalore, India

SystemVerilog RTL

20h

Senior Formal Verification Engineer

Intel Bangalore, India

Verilog System Verilog

20h

Principal Engineer - Validation (ASIC)

Microchip Technology Basking Ridge, New Jersey

ASIC

20h

Senior ATE Hardware Engineer

Lattice Semiconductor Penang, Malaysia

FPGA DFT

20h

Digital Hardware Engineer

BAE Systems Nashua, New Hampshire

FPGA Digital Design

21h

Mixed Signal Design Engineer Intern

Analog Devices Bari, Apulia

Verilog SystemVerilog

21h

Memory Design Engineer

Allegro MicroSystems Milan, Lombardy

Verilog SystemVerilog

21h

Design Methodology – Staff DRAM Power Integrity Engineer

Micron Hyderabad, Telangana

RTL STA

21h

ASIC Reliability Analysis (RA) Engineer

Micron Hyderabad, Telangana

ASIC Verification

21h

SoC Physical Design Formal Verification Engineer, HBM

Micron Multiple locations

Verilog SystemVerilog

21h

HBM Hardware Emulation Engineer

Micron Multiple locations

FPGA RTL

21h

Senior Digital Design Engineer, HBM

Micron Richardson, Texas

Verilog SystemVerilog

21h

Senior Digital Design Engineer, HBM

Micron Richardson, Texas

Verilog SystemVerilog

21h

Staff Engineer, Embedded Sensor Systems & Physical AI

Qualcomm San Diego, California

FPGA ASIC

21h

Sr Staff Engineer - Verification, CI/CD Infrastructure & Embedded Hardware (AISW)

Qualcomm Markham, Ontario

Verification

21h

FPGA Engineer II

CesiumAstro Westminster, Colorado

VHDL Verilog

22h

Senior FPGA Prototyping Engineer

K2 Space United States - Remote

Verilog SystemVerilog

22h

Senior ASIC Physical Design Engineer

K2 Space United States - Remote

ASIC RTL

22h

Senior ASIC Package Design Engineer

K2 Space United States - Remote

ASIC SOC

22h

Senior ASIC Design Verification Engineer

K2 Space United States - Remote

SystemVerilog ASIC

22h

Principal ASIC Synthesis and Timing Engineer

K2 Space United States - Remote

ASIC RTL

22h

Principal ASIC Physical Design Engineer

K2 Space United States - Remote

ASIC RTL

22h

Principal ASIC Package Design Engineer

K2 Space United States - Remote

ASIC SOC

22h

Principal ASIC Design Verification Engineer

K2 Space United States - Remote

SystemVerilog ASIC

22h

Nov. 12, 2026

Director/Sr. Director of Product Management

Axiado San Jose, California

ASIC RTL

1d

Sr. Physical Design Engineer

Qualcomm Santa Clara, California

ASIC RTL

1d

Clock / Power HW Validation Engineer

Qualcomm Tijuana, Baja California

Verilog System Verilog

1d

FY27 Intern - Hardware Design for Post-Quantum Cryptography - 6 months, Sophia

Qualcomm Sophia Antipolis, France

Verilog SystemVerilog

1d

SoC Power Validation Engineer

Qualcomm San Diego, California

ASIC RTL

1d

Mask Layout Design Lead

Qualcomm Markham, Ontario

Digital Design SOC

1d

Staff Analog Mixed Signal/Power Management Design Engineer

Qualcomm San Diego, California

VHDL Verilog

1d

Staff Hardware System Design Engineer

Qualcomm San Diego, California

FPGA ASIC

1d

Implementation Timing / STA Design Engineer

Qualcomm Austin, Texas

ASIC Logic Design

1d

ASIC/SOC Development Engineer, Sr Staff

Qualcomm Bangalore, India

ASIC RTL

1d

Sr Staff Engineer - Hardware Design

Qualcomm Bangalore, India

ASIC SOC

1d

NPU STA/Timing Engineer (Lead/Staff/ Sr Staff)

Qualcomm Bangalore, India

FPGA ASIC

1d

Embedded Software Senior Engineer- SOC Firmware

Qualcomm San Diego, California

ASIC SOC

1d

Staff Engineer – CPUSS Firmware Development

Qualcomm San Diego, California

FPGA RTL

1d

Sr Lead/Staff Engineer - HW Board Design

Qualcomm Bangalore, India

ASIC RTL

1d

ASICS Design Verification Engineer

Qualcomm San Diego, California

SystemVerilog ASIC

1d

STA - Sr Engineer

Qualcomm Chennai, Tamil Nadu

STA Synthesis

1d

Senior Digital Design Engineer - Electronic Warfare Products

CACI Rochester, New York

VHDL Verilog

1d

Senior Design Verification Engineer

Intel Bangalore, India

SystemVerilog RTL

1d

CPU Circuit Design Engineer

Intel Austin, Texas

RTL STA

1d