today

Test Engineer (ATE)

Broadcom San Jose, California

ASIC DFT

13h

Staff IC Verification Engineer

Broadcom Fort Collins, Colorado

VHDL Verilog

13h

ASIC Physical Design Engineer

Broadcom Singapore, Central Singapore

RTL Synthesis

13h

PCIe Design Engineer

Broadcom IND-Bangalore Electronic City - S1

ASIC RTL

13h

PCIe Design Engineer

Broadcom IND-Bangalore Electronic City - S1

ASIC RTL

13h

IC Design Engineer

Broadcom Singapore, Central Singapore

RTL Synthesis

13h

IC Design Engineer

Broadcom Singapore, Central Singapore

RTL Synthesis

13h

R&D Engineer IC Design

Broadcom IND-Bangalore Electronic City - S1

ASIC STA

13h

R&D Engineer IC Design

Broadcom IND-Bangalore Electronic City - S1

ASIC STA

13h

STAFF DFT Engineer

Broadcom IND-Bangalore Electronic City - S1

ASIC STA

13h

STAFF DFT Engineer

Broadcom IND-Bangalore Electronic City - S1

ASIC STA

13h

R&D Engineer IC Design

Broadcom IND-Bangalore Electronic City - S1

ASIC STA

13h

DFT Senior Engineer

Broadcom IND-Bangalore Electronic City - S1

ASIC STA

13h

DFT Senior Engineer

Broadcom IND-Bangalore Electronic City - S1

ASIC STA

13h

DFT Staff Engineer

Broadcom Pune, Maharashtra

ASIC STA

13h

DFT Senior Engineer

Broadcom Pune, Maharashtra

ASIC STA

13h

IC Design Engineer (DFT)

Broadcom Shanghai, Shanghai

ASIC RTL

13h

Senior DFT engineer

Broadcom Singapore, Central Singapore

Verilog ASIC

13h

Senior DFT engineer

Broadcom Singapore, Central Singapore

Verilog ASIC

13h

Senior DFT engineer

Broadcom Singapore, Central Singapore

Verilog ASIC

13h

Senior DFT engineer

Broadcom Singapore, Central Singapore

Verilog ASIC

13h

Senior DFT engineer

Broadcom Singapore, Central Singapore

Verilog ASIC

13h

IC Design Engineer

Broadcom Singapore, Central Singapore

RTL Synthesis

13h

IC Design Engineer

Broadcom Singapore, Central Singapore

ASIC RTL

13h

ASIC Physical Design Engineer

Broadcom Singapore, Central Singapore

RTL Synthesis

13h

Senior Design Formal Verification Engineer

SiFive Multiple locations

VHDL Verilog

13h

CPU Design Verification Engineer II

SiFive Hyderabad, Telangana

SystemVerilog FPGA

13h

FY27 Intern - Qualcomm SoC Engineering Internship - Canada (16 months)

Qualcomm Markham, Ontario

Verilog SystemVerilog

13h

FY27 Intern - Design Verification Engineering Internship - Canada (16 months)

Qualcomm Toronto, Ontario

Verilog SystemVerilog

13h

FY27 Intern - Digital Design Engineering Internship - Canada (16 months)

Qualcomm Toronto, Ontario

Verilog SystemVerilog

13h

Analog Engineer, Staff

Qualcomm Toronto, Ontario

VHDL Verilog

13h

Physical Design Engineer

Qualcomm San Diego, California

ASIC RTL

13h

Silicon Test Engineer, Senior

Qualcomm Tijuana, Baja California

Digital Design DFT

13h

RTL Design(NOC)-Sr Lead Engineer

Qualcomm Bangalore, India

FPGA Verification

13h

Logic Design Engineer

Intel Penang, Malaysia

SystemVerilog RTL

13h

SoC FPGA prototyping

Intel Bangalore, India

VHDL Verilog

13h

CPU HVM Functional-Test Verification Engineer

Intel Penang, Malaysia

Verilog System Verilog

13h

Principal Engineer/Sr. Principal Engineer Digital-RF Subsystems I&T Lead

Northrop Grumman Baltimore, Maryland

VHDL Verilog

13h

Principal/Sr. Principal FPGA Engineer

Northrop Grumman Rolling Meadows, Illinois

VHDL Verilog

13h

FPGA Engineer

Northrop Grumman Rolling Meadows, Illinois

VHDL Verilog

13h

FPGA Development Engineer

HPE Juniper Networks Multiple locations

FPGA RTL

13h

Senior Principal Digital Design Engineer

NXP Semiconductors Noida, Uttar Pradesh

VHDL Verilog

13h

Lead Design Engineer

NXP Semiconductors Noida, Uttar Pradesh

VHDL Verilog

13h

HW/SW System and Application Engineer Intern-Summer 2027

NXP Semiconductors Chandler (Office)

Verilog SystemVerilog

13h

Integrated Circuits Intern

Draper Cambridge, Massachusetts

Verilog System Verilog

14h

Senior DFT ATPG Engineer

NVIDIA Multiple locations

ASIC DFT

14h

ASIC Physical Design Engineer - New College Graduate

NVIDIA Hsinchu, Hsinchu

ASIC RTL

14h

Senior STA Engineer

NVIDIA Tel Aviv, Tel Aviv District

ASIC Static Timing

14h

Physical Design Engineer

NVIDIA Multiple locations

STA Place and Route

14h

Senior Verification Engineer - HSIO Cluster and SOC

NVIDIA Multiple locations

FPGA UVM

14h