today

ASIC Design Engineer

HPE Juniper Networks Bengaluru, Karnataka

VHDL Verilog

1m

Senior Silicon Validation Engineer

IonQ Oxford, England

FPGA ASIC

6m

Senior ASIC Design Engineer - DSP/Analog/SerDes

Celero Communications, Inc. Ottawa, Ontario

Verilog SystemVerilog

20m

Senior ASIC Design Engineer - DSP/Analog/SerDes

Celero Communications, Inc. Irvine, California

Verilog SystemVerilog

20m

Senior ASIC Design Engineer - DSP/Analog/SerDes

Celero Communications, Inc. San Jose, California

Verilog SystemVerilog

20m

Post-Silicon Validation Engineer (Multiple Levels)

Celero Communications, Inc. Multiple locations

ASIC RTL

20m

Research Engineer, Chip Design RL

Anthropic San Francisco, California

FPGA ASIC

21m

Staff Embedded Graphics Software

Ambiq Micro, Inc. Austin, Texas

FPGA SOC

27m

yesterday

ASICS Design Verification Engineer-Senior

Qualcomm San Diego, California

VHDL Verilog

22h

ASICS Engineer

Qualcomm San Diego, California

ASIC RTL

22h

SoC Power Design Engineer

Qualcomm San Diego, California

ASIC RTL

22h

NoC Interconnect Design Engineer and Architect

Qualcomm Santa Clara, California

ASIC RTL

22h

Principal SOC Architect, AI Accelerators (Multiple Locations

Qualcomm Multiple Locations

ASIC SOC

22h

(Sr) Staff SOC Architect - AI Accelerators (Multiple Locations)

Qualcomm Multiple Locations

ASIC SOC

22h

Senior Digital Design Engineer GPU Hardware Design - Athens

Qualcomm Maroúsi, Attica Region

Verilog SystemVerilog

22h

Staff Digital Design Engineer GPU Hardware - Athens

Qualcomm Maroúsi, Attica Region

Verilog SystemVerilog

22h

Senior Software CAD Engineer - Cork, IRL

Qualcomm Cork, Munster

Verilog SystemVerilog

22h

Staff / Senior Staff Engineer - ASIC / NoC SoC deployment architect - Qualcomm - Guyancourt, France

Qualcomm Guyancourt, Île-de-France

ASIC RTL

22h

Senior ASIC Design Verification Engineer - Slingshot

HPE Juniper Networks Bloomington, Minnesota

SystemVerilog FPGA

22h

FPGA Design Engineer

HPE Juniper Networks Spring, Texas

Verilog FPGA

22h

Senior Principal Embedded Software Architect

Analog Devices Multiple locations

Verilog SystemVerilog

22h

Engineer, FPGA Design

Analog Devices Cluj-Napoca, Cluj County

VHDL Verilog

22h

Sr FPGA Design Engineer (NetSec)

Palo Alto Networks Headquarters, California

Verilog SystemVerilog

23h

Engineer II - Hardware

Microchip Technology MA - Beverly Tozer

VHDL Verilog

23h

Engineer II - Verification

Microchip Technology Chennai, Tamil Nadu

Verilog System Verilog

23h

Staff Engineer Electronics

Northrop Grumman Chandler, Arizona

VHDL FPGA

23h

Principal Design Engineer

Micron San Jose, California

RTL STA

23h

Principal Modem PHY IP Design Engineer - Terawave

Blue Origin Multiple locations

FPGA ASIC

23h

Senior Analog Mixed-Signal IC Design Engineer - TeraWave

Blue Origin Multiple locations

SystemVerilog Digital Design

23h

RF Systems FPGA Engineer II - Lunar Permanance

Blue Origin Greater Seattle Area

VHDL Verilog

23h

Principal Engineer, Physical Design

Marvell Hsinchu City

ASIC RTL

23h

Senior Staff Manager, Physical Design

Marvell Hsinchu City

ASIC RTL

23h

Senior Staff, Emulation Engineer

Marvell Bangalore, India

Verilog SystemVerilog

23h

IC Design Engineer

Broadcom Multiple locations

RTL STA

23h

IC Design Engineer

Broadcom Multiple locations

RTL STA

23h

IC Design Engineer

Broadcom Multiple locations

RTL STA

23h

RTL IC Design Engineer

Broadcom Multiple locations

Verilog SystemVerilog

23h

IC Design Engineer

Broadcom Fort Collins, Colorado

Verilog ASIC

23h

Senior Software Engineer, DOCA Verification

NVIDIA Multiple locations

Verification

23h

Physical Verification Engineer

NVIDIA Multiple locations

ASIC SOC

23h

Senior Physical Verification Engineer

NVIDIA Multiple locations

ASIC Verification

23h

Senior Verification Engineer – High Speed Coherent Interconnect Hub

NVIDIA Santa Clara, California

SystemVerilog FPGA

23h

Senior FPGA Prototyping Engineer - Hardware

NVIDIA Santa Clara, California

Verilog System Verilog

23h

SoC Power Management Validation Engineer

Intel Penang, Malaysia

SOC

23h

Logic Design Engineer

Intel Penang, Malaysia

Verilog SystemVerilog

23h

Staff Logic Design Engineer

Intel Penang, Malaysia

Verilog System Verilog

23h

DFT Design Engineering Intern

Intel Penang, Malaysia

Verilog System Verilog

23h

SoC Design Verification Engineer

Intel Santa Clara, California

RTL UVM

23h

Design Verification Graduate Intern 2027

Intel Multiple locations

VHDL Verilog

23h

GPU Physical Design Engineer

Intel San Jose, California

ASIC Static Timing

23h