today

Scaled Synthesis and Processing Technician

AeroVironment WPAFB

Synthesis

3m

Senior Engineer II-Digital Design

Microchip Technology Multiple locations

RTL Digital Design

7m

Senior Engineer I - Digital Verification

Microchip Technology Multiple locations

Verilog SystemVerilog

7m

Senior Engineer, Product Engineering (Prod Dev)

Analog Devices Philippines, Cavite (jp)

VHDL Verilog

18m

Staff Engineer, Systems Design/Architecture Engineering

Analog Devices Multiple locations

RTL SOC

18m

AMS Design Verification Intern

Analog Devices Milan, Lombardy

Verilog System Verilog

18m

Digital Design Engineering Intern

Analog Devices Milan, Lombardy

Verilog System Verilog

18m

CPU Senior Timing Engineer

Intel Bangalore, India

RTL STA

43m

CPU Physical Design Engineer

Intel Bangalore, India

VHDL Verilog

43m

Core Design Verification Engineer

Intel Penang, Malaysia

Verilog System Verilog

43m

Platform Integration Engineer

Intel Santa Clara, California

SystemVerilog RTL

43m

APTM Yield Analysis/Device Engineer

Intel Albuquerque, Mexico

Synthesis DFT

43m

ASIC Design Engineer

HPE Juniper Networks Bengaluru, Karnataka

VHDL Verilog

51m

Senior Silicon Validation Engineer

IonQ Oxford, England

FPGA ASIC

56m

Senior ASIC Design Engineer - DSP/Analog/SerDes

Celero Communications, Inc. Ottawa, Ontario

Verilog SystemVerilog

1h

Senior ASIC Design Engineer - DSP/Analog/SerDes

Celero Communications, Inc. Irvine, California

Verilog SystemVerilog

1h

Senior ASIC Design Engineer - DSP/Analog/SerDes

Celero Communications, Inc. San Jose, California

Verilog SystemVerilog

1h

Post-Silicon Validation Engineer (Multiple Levels)

Celero Communications, Inc. Multiple locations

ASIC RTL

1h

Research Engineer, Chip Design RL

Anthropic San Francisco, California

FPGA ASIC

1h

Staff Embedded Graphics Software

Ambiq Micro, Inc. Austin, Texas

FPGA SOC

1h

yesterday

ASICS Design Verification Engineer-Senior

Qualcomm San Diego, California

VHDL Verilog

23h

ASICS Engineer

Qualcomm San Diego, California

ASIC RTL

23h

SoC Power Design Engineer

Qualcomm San Diego, California

ASIC RTL

23h

NoC Interconnect Design Engineer and Architect

Qualcomm Santa Clara, California

ASIC RTL

23h

Principal SOC Architect, AI Accelerators (Multiple Locations

Qualcomm Multiple Locations

ASIC SOC

23h

(Sr) Staff SOC Architect - AI Accelerators (Multiple Locations)

Qualcomm Multiple Locations

ASIC SOC

23h

Senior Digital Design Engineer GPU Hardware Design - Athens

Qualcomm Maroúsi, Attica Region

Verilog SystemVerilog

23h

Staff Digital Design Engineer GPU Hardware - Athens

Qualcomm Maroúsi, Attica Region

Verilog SystemVerilog

23h

Senior Software CAD Engineer - Cork, IRL

Qualcomm Cork, Munster

Verilog SystemVerilog

23h

Staff / Senior Staff Engineer - ASIC / NoC SoC deployment architect - Qualcomm - Guyancourt, France

Qualcomm Guyancourt, Île-de-France

ASIC RTL

23h

Senior ASIC Design Verification Engineer - Slingshot

HPE Juniper Networks Bloomington, Minnesota

SystemVerilog FPGA

23h

FPGA Design Engineer

HPE Juniper Networks Spring, Texas

Verilog FPGA

23h

Senior Principal Embedded Software Architect

Analog Devices Multiple locations

Verilog SystemVerilog

23h

Engineer, FPGA Design

Analog Devices Cluj-Napoca, Cluj County

VHDL Verilog

23h

Sr FPGA Design Engineer (NetSec)

Palo Alto Networks Headquarters, California

Verilog SystemVerilog

23h

Engineer II - Hardware

Microchip Technology MA - Beverly Tozer

VHDL Verilog

23h

Engineer II - Verification

Microchip Technology Chennai, Tamil Nadu

Verilog System Verilog

23h

Staff Engineer Electronics

Northrop Grumman Chandler, Arizona

VHDL FPGA

1d

Principal Design Engineer

Micron San Jose, California

RTL STA

1d

Principal Modem PHY IP Design Engineer - Terawave

Blue Origin Multiple locations

FPGA ASIC

1d

Senior Analog Mixed-Signal IC Design Engineer - TeraWave

Blue Origin Multiple locations

SystemVerilog Digital Design

1d

RF Systems FPGA Engineer II - Lunar Permanance

Blue Origin Greater Seattle Area

VHDL Verilog

1d

Principal Engineer, Physical Design

Marvell Hsinchu City

ASIC RTL

1d

Senior Staff Manager, Physical Design

Marvell Hsinchu City

ASIC RTL

1d

Senior Staff, Emulation Engineer

Marvell Bangalore, India

Verilog SystemVerilog

1d

IC Design Engineer

Broadcom Multiple locations

RTL STA

1d

IC Design Engineer

Broadcom Multiple locations

RTL STA

1d

IC Design Engineer

Broadcom Multiple locations

RTL STA

1d

RTL IC Design Engineer

Broadcom Multiple locations

Verilog SystemVerilog

1d

IC Design Engineer

Broadcom Fort Collins, Colorado

Verilog ASIC

1d