today

Senior Systems Engineer

CACI Danbury, Connecticut

VHDL FPGA

19h

Software Engineer

Microchip Technology Toronto, Ontario

FPGA Digital Design

19h

ASIC Design Engineer

Microchip Technology Roseville, California

FPGA ASIC

19h

DFT Engineer

Broadcom San Jose, California

Verilog ASIC

19h

ASIC DFT Engineer

Broadcom San Jose, California

Verilog ASIC

19h

ASIC DFT Engineer

Broadcom San Jose, California

Verilog ASIC

19h

Design / DFT Director (NVE Engineering)

Micron Avezzano, Abruzzo

DFT Design for Test

19h

Lead Digital Design Engineer

Analog Devices Limerick, Ireland

Verilog SystemVerilog

19h

Engineer, FPGA Design Engineer

Analog Devices Cluj-Napoca, Cluj County

VHDL Verilog

19h

Aerospace Systems Engineer II - Blue Ring Space Vehicle Requirements & Verification Architect

Blue Origin Multiple locations

Verification

20h

FPGA Electrical Engineer III

Blue Origin Los Angeles, California

Verilog SystemVerilog

20h

FPGA Engineer (Level 2 or 3)

Northrop Grumman Cincinnati, Ohio

VHDL Verilog

20h

Principal Engineer Digital/Sr Principal Engineer Digital

Northrop Grumman Woodland Hills, California

VHDL Verilog

20h

FPGA Digital Engineer - 2

Northrop Grumman Chandler, Arizona

VHDL Verilog

20h

Staff Engineer Digital - RF Subsystems I&T Lead

Northrop Grumman United States-Remote

VHDL Verilog

20h

Principal Server Firmware Architect

SiFive Santa Clara, California

FPGA RTL

20h

Senior Physical Design Engineer

NVIDIA Tel Aviv, Tel Aviv District

STA Place and Route

20h

DFT ATPG Engineer

NVIDIA Multiple locations

DFT Design for Test

20h

Principal Electrical Engineer (Sign on Bonus Available)

BAE Systems Austin, Texas

VHDL FPGA

20h

Principal FPGA (VHDL) Design Engineer (Sign on Bonus Available)

BAE Systems Austin, Texas

VHDL Verilog

20h

Summer 2027 - Electrical Engineering Internship, FPGA

CesiumAstro Melbourne, Florida

VHDL Verilog

20h

Circuit Designer, Space Special Programs

Anduril Chantilly, Virginia

VHDL FPGA

20h

Sr. PCB Designer (Starlink)

SpaceX Bastrop, Texas

FPGA Digital Design

20h

PCB Designer (Starlink)

SpaceX Bastrop, Texas

FPGA Digital Design

20h

yesterday

ASICS Design Engineer, Staff

Qualcomm Hsinchu City, Taiwan

ASIC RTL

1d

ASICS Design Engineer, Senior

Qualcomm Hsinchu City, Taiwan

ASIC RTL

1d

Engineer, CPU Performance Verification

Tenstorrent Multiple locations

RTL Verification

1d

Nov. 8, 2026

Lead Embedded SW Test & Verification Engineer

Blue Origin Greater Seattle Area

HLS Verification

2d

Core to Memory and I/O Engineer | SoC Power Thermal Performance Validation (Temporary position)

Intel Guadalajara, Jalisco

SOC Verification

2d

Cyber Hardware Reverse Engineer

CACI Sterling, Virginia

VHDL Verilog

2d

Camera Subsystem Integration Lead

Qualcomm San Diego, California

Verilog SystemVerilog

2d

Senior Modem Hardware Design Verification Engineer (AI Driven Next Gen Modem Hardware Development)

Qualcomm Boxborough, Massachusetts

VHDL Verilog

2d

FY27 Intern - Digital Design Engineering Intern - Canada (16 months)

Qualcomm Toronto, Ontario

VHDL Verilog

2d

FY27 Intern - RF/Analog Verification Engineering Internship - Canada (4 or 16 months)

Qualcomm Markham, Ontario

Verilog SystemVerilog

2d

SoC Systems Performance Engineer, Senior

Qualcomm San Diego, California

SOC Verification

2d

Heterogeneous Integration Physical Design Engineer

Qualcomm Hsinchu City, Taiwan

ASIC SOC

2d

Advanced Package Design Engineer – Principal Engineer

Qualcomm San Diego, California

DFT SOC

2d

Design Verification WLAN - Sr Engineer

Qualcomm Chennai, Tamil Nadu

Verilog SystemVerilog

2d

NPU AI/Processor Architecture (RTL) Design-Sr Engineer

Qualcomm Bangalore, India

FPGA RTL

2d

ASICS Design Engineer, Senior Staff

Qualcomm Hsinchu City, Taiwan

ASIC RTL

2d

NOC DV Sr Engineer

Qualcomm Bangalore, India

Verilog System Verilog

2d

NOC Design - Sr Engineer

Qualcomm Bangalore, India

ASIC RTL

2d

RTL Design - Sr Engineer

Qualcomm Bangalore, India

ASIC RTL

2d

Nov. 7, 2026

Staff Machine Learning & Silicon Yield Engineer

Broadcom Chandler, Arizona

STA Static Timing

3d

Ethernet NIC System Architecture

Broadcom Multiple locations

Verilog SystemVerilog

3d

DFT Lead Engineer

Broadcom Austin, Texas

Verilog ASIC

3d

DFT Engineer

Broadcom Austin, Texas

Verilog ASIC

3d

DFT Engineer

Broadcom San Jose, California

Verilog ASIC

3d

DFT Engineer

Broadcom San Jose, California

Verilog ASIC

3d

DFT Engineer

Broadcom Austin, Texas

Verilog ASIC

3d