today

Senior ASIC Validation Engineer

Qualcomm Bangalore, India

FPGA ASIC

9h

GPU Design Verification Engineer, Senior

Qualcomm San Diego, California

VHDL Verilog

9h

FY27 Intern - Design For Test for a Secure Asynchronous IP - 6 months, Montbonnot

Qualcomm Montbonnot, France

DFT Design for Test

9h

Senior Design Verification Engineer

Lattice Semiconductor Manila, Metro Manila

SystemVerilog FPGA

9h

SoC Logic Design Engineer

Intel Multiple locations

VHDL Verilog

9h

System and Hardware Enabling Engineer

Intel Bangalore, India

Digital Design DFT

9h

Senior Design Verification Engineer

Intel Multiple locations

SystemVerilog RTL

9h

Junior CPU Verification Engineer

Intel Multiple locations

Verilog System Verilog

9h

Sr SOC Emulation Validation Engineer

Intel Multiple locations

RTL Register Transfer

9h

Sr SOC Emulation Validation Engineer

Intel Multiple locations

SystemVerilog RTL

9h

Principal Senior Engineer - FPGA Design - $20K Sign On Bonus

BAE Systems Westminster, Colorado

VHDL Verilog

9h

Sr. System Design Engineer

Micron Arzano, Campania

Verilog SystemVerilog

9h

Senior Design Engineer – NAND Test (NVE Engineering)

Micron Avezzano, Abruzzo

Digital Design DFT

9h

Staff Engineer - HBM Design Development Technical Leadership

Micron Richardson, Texas

ASIC RTL

9h

Engineer II - Verification

Microchip Technology Chennai, Tamil Nadu

Verilog SystemVerilog

10h

Software Design Engineer II (FPGA)

Microchip Technology Yerevan, Yerevan

FPGA

10h

Principal Engineer - Design

Microchip Technology Hauppauge, New York

VHDL Verilog

10h

DFT Team Manager

Broadcom Austin, Texas

Verilog ASIC

10h

Design Implementation Engineer (Synthesis / STA)

Broadcom Multiple locations

ASIC RTL

10h

Staff Engineer

Broadcom IND-Bangalore Electronic City - S1

Verilog ASIC

10h

Senior Software Engineer - GPU and SOC

NVIDIA Santa Clara, California

SOC Verification

10h

Manager, Software Verification

NVIDIA Yokneam, Israel

Verification

10h

Associate Vice President, Engineering – DCE Connectivity Hardware

Marvell Santa Clara, California

ASIC RTL

10h

Design Verification Intern

Marvell Petah-Tikva

VHDL Verilog

10h

Sr Staff CAD Engineer

Marvell Santa Clara, California

RTL Place and Route

10h

Engineer II - FPGA Verification

BAE Systems Westminster, Colorado

Verilog System Verilog

10h

Senior FPGA Verification Engineer - $30K Sign On Bonus

BAE Systems Westminster, Colorado

Verilog System Verilog

10h

GPU RTL Design Engineer

Apple San Diego, California

11h

Graphics (GPU) RTL Design Engineer

Apple Austin, Texas

Verilog System Verilog

11h

FPGA Designer

Fidus Systems Remote

Remote VHDL Verilog

11h

Principal Engineer, FPGA Architecture

Samsung Semiconductor Folsom, California

Verilog System Verilog

11h

Staff Engineer, Digital ASIC Design — Storage Controllers

SK hynix memory solutions America Inc. San Jose, California

Verilog SystemVerilog

11h

yesterday

Senior Systems Engineer

CACI Danbury, Connecticut

VHDL FPGA

1d

Software Engineer

Microchip Technology Toronto, Ontario

FPGA Digital Design

1d

ASIC Design Engineer

Microchip Technology Roseville, California

FPGA ASIC

1d

DFT Engineer

Broadcom San Jose, California

Verilog ASIC

1d

ASIC DFT Engineer

Broadcom San Jose, California

Verilog ASIC

1d

ASIC DFT Engineer

Broadcom San Jose, California

Verilog ASIC

1d

Design / DFT Director (NVE Engineering)

Micron Avezzano, Abruzzo

DFT Design for Test

1d

Lead Digital Design Engineer

Analog Devices Limerick, Ireland

Verilog SystemVerilog

1d

Engineer, FPGA Design Engineer

Analog Devices Cluj-Napoca, Cluj County

VHDL Verilog

1d

Aerospace Systems Engineer II - Blue Ring Space Vehicle Requirements & Verification Architect

Blue Origin Multiple locations

Verification

1d

FPGA Electrical Engineer III

Blue Origin Los Angeles, California

Verilog SystemVerilog

1d

FPGA Engineer (Level 2 or 3)

Northrop Grumman Cincinnati, Ohio

VHDL Verilog

1d

Principal Engineer Digital/Sr Principal Engineer Digital

Northrop Grumman Woodland Hills, California

VHDL Verilog

1d

FPGA Digital Engineer - 2

Northrop Grumman Chandler, Arizona

VHDL Verilog

1d

Staff Engineer Digital - RF Subsystems I&T Lead

Northrop Grumman United States-Remote

VHDL Verilog

1d

Principal Server Firmware Architect

SiFive Santa Clara, California

FPGA RTL

1d

Senior Physical Design Engineer

NVIDIA Tel Aviv, Tel Aviv District

STA Place and Route

1d

DFT ATPG Engineer

NVIDIA Multiple locations

DFT Design for Test

1d