today

Senior Digital Design Engineer for MEMs ASIC

Analog Devices Milan, Lombardy

Digital Design Verification

17h

Senior Staff Integration Design Engineer

Lattice Semiconductor San Jose, California

Verilog System Verilog

17h

Senior Engineer - Advanced Test Software

BAE Systems Westminster, Colorado

VHDL FPGA

17h

IP Design Verification Engineer - XBAR IP

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

17h

Senior ASIC Design Engineer - XBAR IP

NVIDIA Bengaluru, Karnataka

Verilog FPGA

17h

IP Design Verification Engineer - XBAR IP

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

17h

Senior Chip Architect, Next Gen Networking

NVIDIA Multiple locations

ASIC RTL

17h

Senior IP Design Verification Engineer - XBAR IP

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

17h

Software Verification Engineer

NVIDIA Switzerland, Remote; Switzerland, Zurich

Verification

17h

Senior SOC Verification Engineer - Networking

NVIDIA Bengaluru, Karnataka

Verilog UVM

17h

PCIe Design Verification Intern - Summer 2027

NVIDIA Austin, Texas

SystemVerilog ASIC

17h

PCIe Design Verification Intern - Spring 2027

NVIDIA Santa Clara, California

SystemVerilog ASIC

17h

HBM Media Health Product Engineer (DFT)

Micron Boise, Idaho

DFT

17h

HBM Media Health Product Engineer (DFT)

Micron Boise, Idaho

DFT

17h

Senior Engineer - HIG HBM PSE - Design Validation

Micron Boise, Idaho

VHDL Verilog

17h

Principal Engineer – ASIC SoC Design

Micron Hyderabad, Telangana

Verilog System Verilog

17h

Technical Staff Engineer-Verification

Microchip Technology Bangalore, India

VHDL Verilog

17h

Principal Verification Engineer

Microchip Technology Bangalore, India

VHDL Verilog

17h

Senior Technical Staff Engineer-Verification

Microchip Technology Bangalore, India

VHDL Verilog

17h

Senior Engineer I - Validation (ASIC)

Microchip Technology Basking Ridge, New Jersey

ASIC

17h

Manager Digital Engineering 2

Northrop Grumman San Diego, California

VHDL FPGA

17h

Sentinel - Nuclear Surety - Staff Systems Engineer - 20131

Northrop Grumman Roy, Utah

FPGA ASIC

17h

Staff FPGA Engineer

Northrop Grumman Warner Robins, Georgia

FPGA ASIC

17h

FPGA Digital Engineer - 2

Northrop Grumman Chandler, Arizona

VHDL Verilog

17h

Hardware Engineering Intern

HPE Juniper Networks Sunnyvale, California

Verilog FPGA

17h

Senior HW Digital Design Verification Engineer

NXP Semiconductors Grenoble, Auvergne-Rhône-Alpes

SystemVerilog ASIC

18h

System Level Test Engineer - Staff

Qualcomm San Diego, California

FPGA SOC

18h

Framework Developer Engineer

Qualcomm Tijuana, Baja California

VHDL Verilog

18h

SOC Design Verification Engineer

Qualcomm San Diego, California

Verilog System Verilog

18h

CPU Physical Design CAD Engineer (Sr Staff)

Qualcomm Multiple locations

Digital Design Place and Route

18h

Firmware Development Engineer, Sr. Staff

Qualcomm Multiple locations

FPGA SOC

18h

Director, Automation - Yield Management

Qualcomm San Diego, California

ASIC DFT

18h

BEOL Process Integration Engineer, up to Sr. Staff

Qualcomm Hsinchu City, Taiwan

ASIC SOC

18h

SOC Debug Engineer

Qualcomm San Diego, California

ASIC SOC

18h

PMIC Design Verification Lead (Sr Staff Engineer)

Qualcomm Bangalore, India

Verilog System Verilog

18h

RAS and Manageability Controller Firmware Developer

Qualcomm Bangalore, India

FPGA SOC

18h

CPU Server Physical Design Methodology, Infrastructure and Automation Engineer

Qualcomm Santa Clara, California

STA Place and Route

18h

Silicon Validation Senior Engineer

Qualcomm Bangalore, India

ASIC SOC

18h

SOC Architect / uArchitect

Qualcomm Bangalore, India

SOC Verification

18h

STA Engineer

Qualcomm Santa Clara, California

ASIC RTL

18h

Formal Verification Engineer

Intel Multiple locations

RTL Verification

18h

CPU Clock Design Engineer

Intel Multiple locations

Logic Design STA

18h

Product Failure Analysis Engineer - SCAN Design for Test

Intel Hillsboro, Oregon

DFT Design for Test

18h

Graduate Talent (E-core CPU Physical Design)

Intel Penang, Malaysia

RTL Place and Route

18h

E-Core CPU Design Automation Engineer

Intel Penang, Malaysia

STA Static Timing

18h

Senior Verification Engineer

Intel Leixlip, Leinster

Verilog System Verilog

18h

Memory System Designer and Place and Route Engineer

Broadcom Austin, Texas

Verilog RTL

18h

Memory System Designer and Place and Route Engineer

Broadcom USA-Mendota Heights-Northland

Verilog RTL

18h

Senior Engineer - Test Engineer

AeroVironment San Diego, California

DFT Design for Test

18h

Systems Engineer III — Lunar Human Landing System (HLS)

Blue Origin Multiple locations

HLS Verification

18h