today

ASIC Verification Engineering Intern

HPE Juniper Networks Roseville, California

Verilog SystemVerilog

7h

FY27 Intern - Softip Engineering Co-Op - Canada (4 months)

Qualcomm Ottawa, Ontario

VHDL Verilog

7h

FY27 Intern- Integration of a RISC-V CPU into a Cache-Coherent Emulation Platform - Sophia, 6 months

Qualcomm Bainbridge, Alpes-de-Haute-Provence, France

VHDL Verilog

7h

FY27 Intern- AI-Driven Power Modeling for Evaluating Power Management Mechanisms in NoC Architectures - Guyancourt, 6 months

Qualcomm Guyancourt, Île-de-France

VHDL Verilog

7h

FPGA Prototyping & Physical AI Intern

Lattice Semiconductor Penang, Malaysia

Verilog SystemVerilog

7h

VLSI CAD Timing Intern, Applied AI - Summer 2027

NVIDIA Santa Clara, California

ASIC Digital Design

8h

yesterday

Analog ASIC Design Intern (Summer 2027)

Draper Cambridge, Massachusetts

Verilog System Verilog

1d

Electrical Engineering Internship Summer 2027

BAE Systems Wayne, New Jersey

VHDL Verilog

1d

FY27 Intern - Formal Verification Engineering Internship - 6 months, Cambridge

Qualcomm Cambridge, England

Verilog HDL

1d

FY27 Intern - Camera Design Engineering Internship - Canada (12 or 16 months)

Qualcomm Vancouver, British Columbia

Verilog System Verilog

1d

Oct. 28, 2026

Design Verification- Intern

Marvell IL - Petah Tikva

Verilog System Verilog

2d

Intern, RTL Power Macromodeling Engineer

Samsung Semiconductor San Jose, California

Verilog SystemVerilog

2d

Intern, Power-Thermal Simulation Software Engineer

Samsung Semiconductor San Jose, California

Verilog SystemVerilog

2d

2027 Internship - Formal Verification Engineer

Cirrus Logic Austin, Texas

Verilog System Verilog

2d

Oct. 27, 2026

Hardware Engineering Intern

HPE Juniper Networks Sunnyvale, California

FPGA ASIC

3d

Oct. 24, 2026

Design Verification Engineering Intern

Analog Devices Edinburgh, South Carolina

VHDL Verilog

6d

Design Verification Engineering Intern

Analog Devices Newbury, England

VHDL Verilog

6d

AI Hardware Engineering Intern

Intel Multiple locations

FPGA ASIC

6d

Oct. 23, 2026

ASIC Engineering Intern

HPE Juniper Networks Durham, North Carolina

ASIC Verification

7d

FY27 Intern - Applied AI Engineering Intern (Hardware Systems) - Canada (16 months)

Qualcomm Vancouver, British Columbia

Verilog SystemVerilog

7d

FY27 Intern - Camera Design Implementation Intern - Canada (16 months)

Qualcomm Vancouver, British Columbia

ASIC RTL

7d

Oct. 22, 2026

Design Engineer Intern

Marvell Yokneam

RTL SOC

8d

FY27 Intern - Edge AI and Display Hardware Architecture Development Engineering Internship - Canada (16 months)

Qualcomm Markham, Ontario

VHDL Verilog

8d

AMS Design Verification Intern

Analog Devices Milan, Lombardy

Verilog System Verilog

8d

Digital Design Engineering Intern

Analog Devices Milan, Lombardy

Verilog System Verilog

8d

Oct. 21, 2026

DFT Design Engineering Intern

Intel Penang, Malaysia

Verilog System Verilog

9d

Design Verification Graduate Intern 2027

Intel Multiple locations

VHDL Verilog

9d

ASIC Design Intern

SK hynix memory solutions America Inc. San Jose, California

Verilog SystemVerilog

9d

Oct. 20, 2026

ASIC TOP Floorplan Intern, 2027

NVIDIA Shanghai, Shanghai

Verilog System Verilog

10d

ASIC Verification Intern - Summer 2027

NVIDIA Toronto, Ontario

Verilog SystemVerilog

10d

Intern - Design Engineer, HBM

Micron Richardson, Texas

VHDL Verilog

10d

Intern - Design Engineer, HBM

Micron Richardson, Texas

VHDL Verilog

10d

Intern - Design Engineer, HBM

Micron Richardson, Texas

Verilog SystemVerilog

10d

Analog/Mixed Signal Design Intern

Analog Devices Newbury, England

Verilog Digital Design

10d

ASIC Intern

HPE Juniper Networks Roseville, California

Verilog SystemVerilog

10d

2027 Summer Avionics Electrical Engineer Intern

Ursa Major Berthoud, Colorado

FPGA ASIC

10d

Oct. 16, 2026

2027 Internship - Systems Engineering - Power & Control

Cirrus Logic Austin, Texas

VHDL Verilog

14d

Oct. 14, 2026

VLSI Design Verification Masters Level Intern

HPE Juniper Networks Ft. Collins, Colorado, United States of America

VHDL Verilog

16d

Physical Design Intern - Master's Degree

Marvell Singapore, Central Singapore

ASIC RTL

16d

Design Verification- Intern

Marvell Petah-Tikva

Verilog System Verilog

16d

Oct. 13, 2026

System Software Engineering Intern, GPU and SOC - Summer 2027

NVIDIA Taipei, Taipei

SOC

17d

DFT Intern - 2027

NVIDIA Shanghai, Shanghai

Verilog Logic Design

17d

VLSI Logic Design Intern

HPE Juniper Networks Chippewa Falls, Wisconsin, United States of America

Verilog System Verilog

17d

ASIC Verification Engineering Intern

HPE Juniper Networks Roseville, California

Verilog SystemVerilog

17d

VLSI Design Verification Intern

HPE Juniper Networks Ft. Collins, Colorado, United States of America

VHDL Verilog

17d

VLSI Logic Design Intern

HPE Juniper Networks Ft. Collins, Colorado, United States of America

Verilog System Verilog

17d

ASIC Intern

HPE Juniper Networks Sunnyvale, California

VHDL Verilog

17d

Oct. 10, 2026

AI-Driven Physical Design Engineering (PhD Intern)

Intel Multiple locations

RTL Digital Design

20d

ASIC Engineer Intern

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

20d

Oct. 9, 2026

ASIC Verification/Design Engineering Intern

HPE Juniper Networks Roseville, California

Verilog ASIC

21d