FE Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. APPLE INC has the following available in San Diego, California. Microarchitecture definition. RTL design in SystemVerilog/Verilog. IP integration and verification. RTL low-power design and running tool for RTL power analysis. Running tools to ensure lint-free and CDC clean design. Synthesis and timing constraints. Collaboration with system/algorithm and firmware team to ensure performance and power efficiency. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $156,956 - $214,300/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, Communication Engineering, or a related field and 3 years of experience in the job offered or related occupation. Experience and/or education must include: Utilizing System Verilog or Verilog to write RTL for the high-speed communication IPs. Utilizing Scripting language (Python, Perl,TCL), including automating the RTL integration and verification, synthesis and timing analysis. Utilizing CDC, RDC tools/techniques, and knowledge of multiple clock domains, multiple reset domains to fix issues. Experience in RTL Design with complex FSMs and power saving features. Experience in IP Integration including clock/reset module design, clock gating implementation, fabric/bus system configuration and design. Low power design concepts and implementation including clock gating, power gating, and DVFS. High speed interface knowledge and design(AXI/AHB bus and peripherals). Utilizing Synthesis tools from Synopsys, Cadence and setting the constraints, and knowledge of LEC/LEQ. Understanding of computer architecture and SOC’s. Knowledge of and experience with wireless communication.