SOC Design Verification Engineer

Apple’s wireless chip powers connectivity across every new iPhone — and its successor is already taking shape. Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization owns every aspect of wireless silicon development, with a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level. It is driven by a world-class, vertically integrated team spanning RF/Analog, Systems/PHY/MAC, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. As a Wireless SOC Design Verification Engineer, you’ll be at the heart of the chip design effort — owning a meaningful verification scope and growing it project to project. You’ll be responsible for pre-silicon RTL verification at the block, subsystem, and top-level SOC, taking your scope from test planning through coverage closure and signoff. Working closely with architects, designers, and firmware engineers, you’ll build reusable testbenches and verification environments using modern, metric-driven methodology. Areas you may work on include the Power Management Unit, CPU subsystem, DMA, on-chip debug infrastructure, PCIe, bus fabric, boot and secure-boot sequencing, MAC-PHY Verification, Radio integration, and peripherals such as SPI — choosing simulation, formal, or whichever approach the design actually calls for. Low power is part of your scope wherever it shows up: you’ll verify power intent using UPF within your area. Over time, you can grow deeper into the IPs and subsystems you know best, or broader — across IPs and up from block level to full SOC integration. The team is also pushing hard on AI-assisted verification, and you’ll help figure out where it fits best: test generation, debug, coverage closure, or all the above. BS and a minimum of 10 years relevant industry experience. Hands-on experience across the verification cycle: test planning, testbench implementation, test creation and debug, and coverage closure. Strong SystemVerilog and Verilog skills, with solid working knowledge of UVM. Solid problem-solving and debugging skills with constrained-random verification. Understanding of digital logic design, SOC architecture, and microarchitecture.