Senior PnR (Place and Route) Engineer

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Omni Design Technologies

Bangalore , Indiana , United States
VHDL Verilog RTL Place and Route SOC IP Design Verification
Apply Now Posted July 28, 2026 Please mention FPGAjobs in your application — it helps a lot!
We are looking for an experienced place-and-route engineer, who is capable of driving the required digital backend flows to create our designs. The ability to work closely with rtl design team to understand partition architecture and drive physical aspects early in design cycle in a key feature of this role!
Qualifications
  • You should have physical design experience, with recent successful tapeouts in deep submicron technology and FinFet technology.
  • Knowledgeable in partition level P&R implementation, including floorplanning, clock & power distribution, timing closure, physical & electrical verification
  • Strong knowledge of PD construction & analysis flows and methodology
  • Ability to execute to stringent schedule & die size requirements
  • Strong communication skills
  • Experienced in industry standard tools, understand their capabilities and underlying algorithms
  • Experience with large SOC/IP designs with frequencies in excess of 500Mhz
  • Ability to resolve design and flow issues related to physical design, identify potential solutions and drive execution
    • Education and Experience
  • B.E./B.Tech./M.E./M.Tech in VLSI
  • Minimum of 5 years of working experience in PnR flow of a product company.
  • Candidate must have working experience in 16nm FF and on lower nodes.
    • Detailed responsibilities and skills
  • Perform Floor-planning and Placement, CTS, Routing.
  • LVS, DRC and Antenna checks and Generation of GDSII and .lib
  • Reliability checks like EM violations check and Signal Integrity issues like crosstalk
  • Perform physical verification, IR drop analysis, and generating SPEF
  • Knowledge of full RTL to GDSII flow (Floorplan, CTS, PnR, DRC/LVS, SI, IR Drop )
  • Hands-on experience with Cadence PnR tools, Floorplanning, IR Drop and Physical verification
  • Shave good understanding of verilog/VHDL
  • Exposure to low power techniques
  • Knowledge of tcl and Python scripting is a must

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