DFT Jobs in California

Sr. Principle VLSI/ ASIC Design Engineer

HPE Juniper Networks Sunnyvale, California

Verilog System Verilog

1mo

Design For Test Intern, MS - Summer 2027

Marvell Santa Clara, California

Verilog System Verilog

1mo

Senior Hardware Test Engineer

Qualcomm San Diego, California

DFT Design for Test

1mo

Principal DFT Engineer

Celero Communications, Inc. Irvine, California

Verilog SystemVerilog

1mo

Electrical Test Engineer

Anduril Santa Ana, California

FPGA RTL

1mo

Senior DFT Logic Design Engineer

Intel Multiple locations

ASIC RTL

1mo

Infra Systems Physical Architect

Qualcomm San Diego, California

ASIC Place and Route

1mo

Senior DFT Engineer

NVIDIA Multiple locations

RTL DFT

1mo

Physical Design Engineer (Silicon Engineering)

SpaceX Palo Alto, California

ASIC RTL

1mo

Physical Design Engineer (Silicon Engineering)

SpaceX Irvine, California

ASIC RTL

1mo

Senior System Integration and Validation Engineer

NVIDIA Santa Clara, California

Logic Design DFT

1mo

ASIC Design Engineer – Clocks IP

NVIDIA Multiple locations

Verilog ASIC

1mo

Physical Design CPU Methodology Engineer

Tenstorrent Santa Clara, California

ASIC RTL

1mo

Hardware System Design Engineer, Senior or Staff

Qualcomm San Diego, California

FPGA ASIC

1mo

ASIC/RTL Design Engineer for High-speed Interfaces

Qualcomm San Diego, California

ASIC RTL

1mo

CPU SRAM Design & Layout Engineer

Qualcomm Santa Clara, California

Verilog Static Timing

1mo

Senior Staff Engineer, Diagnostics and AI

Qualcomm San Diego, California

ASIC DFT

1mo

Senior Principal ASIC Implementation Engineer

BAE Systems Multiple locations

ASIC Static Timing

1mo

SoC Systems & Infrastructure Engineer (Design • Validation • Debug • FPGA • Emulation • Software)

Qualcomm San Diego, California

Verilog SystemVerilog

1mo

Design for Test Intern, BS - Summer 2027

Marvell Multiple locations

UVM DFT

1mo