UVM Jobs in Santa Clara, CA

Sr. Staff Design Verification Engineer

d-Matrix Multiple locations

Remote SystemVerilog ASIC

1mo

Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU

NVIDIA Multiple locations

Verilog SystemVerilog

1mo

GPU Verification Engineer - New College Grad 2026

NVIDIA Multiple locations

FPGA ASIC

1mo

Senior ASIC Design Verification Engineer

Palo Alto Networks Santa Clara, California

SystemVerilog ASIC

1mo

Senior Design Verification Engineer

Intel Santa Clara, California

SystemVerilog FPGA

1mo

Mixed Signal validation engineer

Intel Multiple locations

Verilog System Verilog

1mo

Senior Verification Engineer - Hardware

NVIDIA Santa Clara, California

VHDL Verilog

1mo

Senior ASIC Verification Engineer

NVIDIA Multiple locations

SystemVerilog ASIC

1mo

Custom SOC IP Verification Engineer

NVIDIA Multiple locations

SystemVerilog ASIC

1mo

Senior ASIC Design Engineer - DFX

NVIDIA Santa Clara, California

Verilog ASIC

1mo

Senior Verification Engineer

NVIDIA Santa Clara, California

Verilog SystemVerilog

1mo

Senior Memory Controller Verification Engineer

NVIDIA Santa Clara, California

Verilog System Verilog

1mo

ASIC Verification Engineer

NVIDIA Santa Clara, California

Verilog System Verilog

1mo

Senior ASIC Verification Engineer

NVIDIA Multiple locations

Verilog System Verilog

1mo

ASIC Verification Engineer

NVIDIA Santa Clara, California

SystemVerilog ASIC

1mo

Senior Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog RTL

1mo

Senior Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog RTL

1mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

1mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

1mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

1mo