UVM Jobs in Santa Clara, CA

Front End Design Verification Engineer

Tenstorrent Santa Clara, California

SystemVerilog ASIC

7h

ASIC Design Verification Engineer (Santa Clara, CA)

Qualcomm Santa Clara, California

Verilog SystemVerilog

2d

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

2d

Senior Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog RTL

2d

Design Verification Engineer

Intel Santa Clara, California

SystemVerilog FPGA

5d

Sr. Staff Engineer, SoC Design Verification

Tenstorrent Multiple locations

UVM SOC

6d

Senior Firmware Verification and Bringup Engineer

NVIDIA Santa Clara, California

SystemVerilog RTL

7d

Design for Test Intern, BS - Summer 2027

Marvell Multiple locations

UVM DFT

11d

Design Verification Intern, BS - Summer 2027

Marvell Multiple locations

VHDL ASIC

11d

Design Verification Intern, MS - Summer 2027

Marvell Multiple locations

VHDL ASIC

11d

Sr. Staff Engineer, Front-End Verification

Tenstorrent Multiple locations

SystemVerilog RTL

11d

ASIC Design Verification Engineer (Santa Clara, CA)

Qualcomm Santa Clara, California

Verilog SystemVerilog

12d

Senior Design Verification Engineer - Neuromorphic Computing

Intel Multiple locations

ASIC RTL

14d

Senior Verification Engineer, SoC

NVIDIA Multiple locations

Verilog System Verilog

15d

GPU Design Verification Engineer

Qualcomm Multiple locations

VHDL Verilog

15d

Design Verification Engineer — Memory Subsystem

Qualcomm Santa Clara, California

Verilog SystemVerilog

18d

Sr. Engineer, SoC Design Verification Engineer, System Management Controller

Tenstorrent Multiple locations

SystemVerilog UVM

20d

NVIDIA 2027 Internships: Hardware Verification

NVIDIA Santa Clara, California

VHDL Verilog

26d

NVIDIA 2027 Internships: Hardware ASIC Design

NVIDIA Santa Clara, California

VHDL Verilog

26d

Senior ASIC Verification Engineer

NVIDIA Santa Clara, California

ASIC UVM

26d