Sept. 22, 2026

Digital IC Design Intern, MS - Summer 2027

Marvell Multiple locations

Verilog ASIC

1mo

Sept. 19, 2026

FY27 Intern - MSIP Digital Design Verification Engineering Internship - Canada (16 months)

Qualcomm Toronto, Ontario

VHDL Verilog

1mo

FY27 Intern - MSIP Digital Design Engineering Internship - Canada (16 months)

Qualcomm Toronto, Ontario

Verilog System Verilog

1mo

RF/Analog Design/Mixed-Signal Engineering Internship – Summer 2027

Qualcomm Multiple locations

Verilog SystemVerilog

1mo

Hardware (CPU, GPU, SoC, Digital Design, DV) Engineering Internship – Summer 2027

Qualcomm Multiple Locations

Verilog SystemVerilog

1mo

Sept. 18, 2026

Design For Test Intern, MS - Summer 2027

Marvell Santa Clara, California

Verilog System Verilog

1mo

Sept. 17, 2026

FY27 Intern - Low-Power AI, Audio, and Sensors Subsystem Engineering Internship - ASIC Design / Verification/Implementation - Canada (12 or 16 months)

Qualcomm Markham, Ontario

Verilog System Verilog

1mo

FY27 Intern - Low-Power AI, Audio, and Sensors Subsystem Engineering Internship - ASIC Firmware / Embedded - Canada (12 or 16 months)

Qualcomm Markham, Ontario

FPGA ASIC

1mo

Architecture Energy Modeling Engineering Intern - 2027

NVIDIA Shanghai, Shanghai

Verilog ASIC

1mo

Power Analysis and Optimization Intern - 2027

NVIDIA Shanghai, Shanghai

ASIC RTL

1mo

Custom SOC Intern - 2027

NVIDIA Shanghai, Shanghai

Verilog System Verilog

1mo

Sept. 15, 2026

Silicon Design - Flows and Methodology Intern

Intel Guadalajara, Jalisco

Verilog System Verilog

1mo

NVTHERM SoC Verification Intern, Tegra - 2027

NVIDIA Shanghai, Shanghai

Verilog SystemVerilog

1mo

Sept. 12, 2026

FY27 Intern - Display IP Engineering Internship - Canada (16 months)

Qualcomm Markham, Ontario

VHDL Verilog

1mo

FY27 Intern - Compute DSP/AI Processor Engineering Internship - Canada (16 months)

Qualcomm Markham, Ontario

VHDL Verilog

1mo

Silicon Co-design Intern - 2027

NVIDIA Shanghai, Shanghai

ASIC Digital Design

1mo

Ph.D. Intern - Architecture, DSP & Systems Architecture

Marvell Multiple locations

Verilog SystemVerilog

1mo

Sept. 11, 2026

Engineering Intern (EE/CE/RF), Summer 2027 (Hybrid)

BAE Systems Nashua, New Hampshire

VHDL Verilog

1mo

Sept. 10, 2026

Intern - Engineering (ASIC Verification)

Microchip Technology San Jose, California

Verilog SystemVerilog

1mo

Summer 2027 Internships - Design Engineering

Silicon Labs Austin, Texas

VHDL Verilog

1mo

Digital IC Design Engineer, Intern

Marvell Pavia, Lombardy

Digital Design Static Timing

1mo

Sept. 5, 2026

FY27 Intern - Engineering Internship 2027 - 6 months, Cork

Qualcomm Cork, Munster

VHDL Verilog

1mo

Design for Test Intern, BS - Summer 2027

Marvell Multiple locations

UVM DFT

1mo

Functional Validation Intern, BS - Summer 2027

Marvell Multiple locations

FPGA ASIC

1mo

Design Verification Intern, BS - Summer 2027

Marvell Multiple locations

VHDL ASIC

1mo

Design Verification Intern, MS - Summer 2027

Marvell Multiple locations

VHDL ASIC

1mo

Physical Design Engineer Intern, BS - Summer 2027

Marvell Multiple locations

ASIC RTL

1mo

Physical Design Engineer Intern, MS - Summer 2027

Marvell Multiple locations

ASIC RTL

1mo

ASIC Design and Verification Intern, SOC - 2027

NVIDIA Shanghai, Shanghai

Verilog SystemVerilog

1mo

SOC Design Team Methodology Intern - 2027

NVIDIA Shanghai, Shanghai

ASIC SOC

1mo

Intel NPU Internship

Intel Leixlip, Leinster

FPGA RTL

1mo

Sept. 4, 2026

Pre-Silicon Diagnostics Intern

HPE Juniper Networks Ft. Collins, Colorado, United States of America

FPGA ASIC

1mo

ASIC Firmware and Diagnostic Intern

HPE Juniper Networks Bloomington, Minnesota

ASIC

1mo

Sept. 3, 2026

Silicon Hardware Engineering - Intern, Graduate

Intel Multiple locations

Logic Design DFT

1mo

Silicon Hardware Engineering - Intern, Bachelor’s

Intel Multiple locations

Logic Design DFT

1mo

Interim Engineering Intern_2027_HW

Qualcomm Multiple locations

VHDL Verilog

1mo

2026 Intern-Digital Design/Verification Engineer

Qualcomm Shanghai, Shanghai

ASIC RTL

1mo

2026 Intern-Physical Design Engineer

Qualcomm Shanghai, Shanghai

Verilog Synthesis

1mo

2026 Intern-Embedded SW Engineer(SOC)

Qualcomm Shanghai, Shanghai

SOC

1mo

Sept. 2, 2026

Design Verification Engineer (RDSS Intern)

NVIDIA Hsinchu, Hsinchu

SystemVerilog RTL

1mo

Sept. 1, 2026

SSD Firmware Development Engineer Intern

SK hynix memory solutions America Inc. San Jose, California

FPGA ASIC

2mo

Hardware Engineer Internship - Summer 2027

Hudson River Trading New York, NY, United States

SystemVerilog FPGA

2mo

Aug. 31, 2026

FY27 Intern - CPU Engineering Internship 2027 - 6 months, Cork

Qualcomm Cork, Munster

Verilog System Verilog

2mo

Aug. 26, 2026

ASIC Engineering Intern, Networking Chip Design - 2027

NVIDIA Shanghai, Shanghai

RTL Verification

2mo

ASIC Physical Design Intern - 2027

NVIDIA Shanghai, Shanghai

ASIC RTL

2mo

Aug. 25, 2026

Digital Design Engineer Intern

Analog Devices Multiple locations

VHDL Verilog

2mo

ASIC Physical Design Engineer (RDSS Intern)

NVIDIA Hsinchu, Hsinchu

ASIC RTL

2mo

ASIC Physical Design Intern - 2027

NVIDIA Hsinchu, Hsinchu

ASIC RTL

2mo

Aug. 20, 2026

System Software Engineer – GPU and SOC (2027 RDSS Intern)

NVIDIA Taipei, Taipei

SOC

2mo

NVIDIA 2027 Internships: Mixed Signal Design

NVIDIA Santa Clara, California

VHDL Verilog

2mo