UVM Jobs

Browse open UVM positions for FPGA, ASIC, and RTL engineers.

All Locations California 140 Bangalore 74 Texas 59 Austin, TX 57 Santa Clara, CA 49 Telangana 38 Hyderabad 38 Karnataka 33

Staff Engineer, Design Verification Engineering

Analog Devices Bangalore, India

SystemVerilog RTL

1mo

Staff Design Verification Engineer

Analog Devices Bangalore, India

Verilog SystemVerilog

1mo

Senior Verification Engineer

Analog Devices Wilmington, Massachusetts

Verilog SystemVerilog

1mo

Principal Engineer, Design Verification

Analog Devices Multiple locations

Verilog SystemVerilog

1mo

Mixed Signal Design Verification Engineer

Analog Devices Wilmington, Massachusetts

SystemVerilog RTL

1mo

Staff Digital Verification Engineer

Analog Devices Singapore, Central Singapore

SystemVerilog RTL

1mo

Digital Verification Lead

Analog Devices Singapore, Central Singapore

SystemVerilog UVM

1mo

Staff Design Verification Engineer – SoC and eFPGA

Analog Devices San Jose, California

Verilog SystemVerilog

1mo

SoC Verification Engineer

Intel Bangalore, India

RTL UVM

1mo

Sr. Staff Design Verification Engineer

d-Matrix Multiple locations

Remote SystemVerilog ASIC

1mo

Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU

NVIDIA Multiple locations

Verilog SystemVerilog

1mo

Principal Mixed Signal Design Verification, Team Lead

Allegro MicroSystems Musselburgh, Scotland

SystemVerilog UVM

1mo

Sr Principal Digital Design Engineer

NXP Semiconductors San Jose, California

Verilog SystemVerilog

1mo

Principal Digital Verification Engineer

NXP Semiconductors Chandler (Office)

Verilog SystemVerilog

1mo

Principal Analog Mixed Signal Verification Engineer

NXP Semiconductors Chandler (Office)

Verilog SystemVerilog

1mo

Staff Design Verification Engineer

Cerebras Systems Sunnyvale, California

SystemVerilog RTL

1mo

Senior ASIC verification engineer

HPE Juniper Networks Roseville, California

Verilog System Verilog

1mo

Design Verification Manager

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

1mo

AIML enhanced Design/Verification Methodology Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog FPGA

1mo

Senior Design Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog FPGA

1mo

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