UVM Jobs

Senior ASIC Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

1mo

ASIC Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

1mo

GPU Verification Engineer - New College Grad 2026

NVIDIA Multiple locations

FPGA ASIC

1mo

Manager, DFT - Post Silicon

NVIDIA Tel Aviv, Tel Aviv District

Verilog RTL

1mo

Mixed Signal Design Verification (MSDV) Engineer

Nexperia Dallas, Texas

Verilog SystemVerilog

1mo

Senior ASIC Design Verification Engineer

Palo Alto Networks Santa Clara, California

SystemVerilog ASIC

1mo

Senior USB IP Design Verification Engineer

Intel Multiple locations

Verilog System Verilog

1mo

Senior Design Verification Engineer

Intel Santa Clara, California

SystemVerilog FPGA

1mo

CPU Verification Engineer

Intel Austin, Texas

SystemVerilog RTL

1mo

IP RTL Senior Design Engineer

Intel Bangalore, India

Verilog System Verilog

1mo

CPU Verification Engineer

Intel Multiple locations

VHDL Verilog

1mo

Mixed Signal validation engineer

Intel Multiple locations

Verilog System Verilog

1mo

SoC/IP Design Verification Engineer

Intel Multiple locations

SystemVerilog FPGA

1mo

Senior Engineer – ASIC Verification (m/f/d)

Microchip Technology Dresden, Saxony

SystemVerilog FPGA

1mo

Senior Technical Staff Engineer - Verification

Microchip Technology Chandler, Arizona

Verilog SystemVerilog

1mo

Technical Staff Engineer - Emulation

Microchip Technology Burnaby, British Columbia

ASIC UVM

1mo

Sr. Engineer II – Verification

Microchip Technology Bangalore, India

VHDL Verilog

1mo

Director, Design Engineering – Data Center Solutions (DCS)

Microchip Technology Bangalore, India

Verilog SystemVerilog

1mo

Technical Staff Engineer - Emulation

Microchip Technology Multiple locations

ASIC UVM

1mo

Principal Engineer - Verification

Microchip Technology Chennai, Tamil Nadu

Verilog System Verilog

1mo