today

Engineer/Principal Engineer Systems-17346

Northrop Grumman Roy, Utah

VHDL Verilog

7h

Systems Engineer -20539

Northrop Grumman Roy, Utah

VHDL Verilog

7h

Principal/Sr Principal Engineer Systems-17345

Northrop Grumman Roy, Utah

VHDL Verilog

7h

Staff / Principal - Memory Circuit Design Verification

Micron Hyderabad, Telangana

Verification

7h

New College Grad - HBM Verification

Micron Jalisco, Chiapas

Verilog RTL

7h

HBM SoC RTL Design Engineer

Micron Richardson, Texas

Verilog SystemVerilog

7h

Staff Engineer, ASIC Digital Design

Micron Minneapolis, Minnesota

SystemVerilog ASIC

7h

Staff - HIG HBM Architecture

Micron Richardson, Texas

Verilog SystemVerilog

7h

Firmware Engineer

NVIDIA Multiple locations

VHDL Verilog

7h

Custom SOC ASIC Engineer - New College Grad 2027

NVIDIA Shanghai, Shanghai

Verilog System Verilog

7h

Power Methodology and Analysis Engineer

NVIDIA Shanghai, Shanghai

Verilog ASIC

7h

VLSI CAD Timing Intern, Applied AI - Summer 2027

NVIDIA Santa Clara, California

ASIC Digital Design

7h

Senior Staff Digital Design Engineer - Audio DSP Algorithm

Syntiant Rapperswil-Jona, St. Gallen, Switzerland

Verilog System Verilog

7h

Software Patch Verification Engineer

Two Six Tech Linthicum, Maryland

Verification

7h

yesterday

Principal/Sr. Principal Engineer Systems-20424

Northrop Grumman Roy, Utah

VHDL Verilog

1d

Sr. Principal Electrical Engineer (FPGA Design Engineer)

Northrop Grumman San Diego, California

FPGA UVM

1d

Staff FPGA Digital Engineer - 5

Northrop Grumman Chandler, Arizona

VHDL Verilog

1d

Principal Engineer, Design

Micron Tokyo, Tokyo

RTL STA

1d

Engineer - HIG HBM - PE Design Validation

Micron Singapore, Central Singapore

VHDL Verilog

1d

HBM SoC Physical Design Engineer

Micron Richardson, Texas

RTL STA

1d

Senior Engineer Design

Micron Hyderabad, Telangana

Verilog RTL

1d

Principal Design Engineer, HBM Architecture

Micron Richardson, Texas

RTL STA

1d

Sr/ Staff Design Engineer/Architect(Datapath), HBM

Micron Richardson, Texas

RTL STA

1d

Analog ASIC Design Intern (Summer 2027)

Draper Cambridge, Massachusetts

Verilog System Verilog

1d

Principal Engineer - Design for Test

Microchip Technology Bangalore, India

1d

Senior Engineer I-Design • FPGA Applications

Microchip Technology Hyderabad, Telangana

FPGA SOC

1d

Principal Senior Engineer - FPGA Design - $30K Sign On Bonus

BAE Systems Westminster, Colorado

VHDL Verilog

1d

Senior FPGA Design Engineer - $30K Sign On Bonus

BAE Systems Westminster, Colorado

VHDL Verilog

1d

Engineer II - FPGA Verification

BAE Systems Westminster, Colorado

VHDL Verilog

1d

Principal Electrical Engineer (Sign on Bonus)

BAE Systems Multiple locations

VHDL Verilog

1d

Electrical Engineering Internship Summer 2027

BAE Systems Wayne, New Jersey

VHDL Verilog

1d

Integration Design Engineer

Lattice Semiconductor Manila, Metro Manila

Verilog System Verilog

1d

FY27 Intern - Formal Verification Engineering Internship - 6 months, Cambridge

Qualcomm Cambridge, England

Verilog HDL

1d

SOC Verification and Methodology Engineer

Qualcomm San Diego, California

Verilog SystemVerilog

1d

GPU Design Verification Engineer, Senior

Qualcomm San Diego, California

VHDL Verilog

1d

FY27 Intern - Camera Design Engineering Internship - Canada (12 or 16 months)

Qualcomm Vancouver, British Columbia

Verilog System Verilog

1d

High-Speed Analog & Mixed-Signal PHY Design Engineer

Qualcomm San Diego, California

VHDL Verilog

1d

CPU Physical Design Engineer (Lead/Staff/Sr. Staff)

Qualcomm Bangalore, India

FPGA RTL

1d

ASIC RTL Design Engineer (Sr. Engr / Sr. Lead Engr)

Qualcomm Bangalore, India

Verilog ASIC

1d

NOC DV Assoc Engineer

Qualcomm Bangalore, India

Verilog System Verilog

1d

Design Verification (NPU) - Sr Lead Engineer

Qualcomm Bangalore, India

FPGA ASIC

1d

RTL Design (NPU) - Sr Lead

Qualcomm Bangalore, India

FPGA Verification

1d

FPGA Prototyping Engineer

Intel Penang, Malaysia

FPGA RTL

1d

FPGA Prototyping Engineer

Intel Penang, Malaysia

Verilog System Verilog

1d

Sr. MSIAM SOC Engineer (Unit 42)

Palo Alto Networks Charlotte, North Carolina

SOC

1d

Software Verification Engineer

NVIDIA Raanana, Israel

Verification

1d

Architecture Energy Modeling Engineer

NVIDIA Shanghai, Shanghai

Verilog ASIC

1d

Software Verification Engineer

NVIDIA Yokneam, Israel

Verification

1d

Senior CPU Power Architect

NVIDIA Santa Clara, California

ASIC RTL

1d

Senior Physical Design Methodology Engineer, PPA Improvement Technology Scaling

NVIDIA Multiple locations

Place and Route SOC

1d