yesterday

Working Student (f/m/d) Digital Physical Design

NXP Semiconductors Dresden

VHDL SystemVerilog

1d

Technical Director - FE

NXP Semiconductors Noida, Uttar Pradesh

ASIC RTL

1d

Physical Design Lead

NXP Semiconductors Bangalore, India

ASIC RTL

1d

Staff Design Verification Engineer, AI Hardware

Tenstorrent Belgrade, Central Banat District

RTL UVM

1d

Senior Design Verification Engineer, AI Hardware

Tenstorrent Belgrade, Central Banat District

SystemVerilog RTL

1d

Principal FPGA Design Engineer

Terran Orbital Irvine, California

VHDL SystemVerilog

1d

Group Lead, Firmware & Software

HRL Laboratories Calabasas, California

VHDL Verilog

1d

Oct. 28, 2026

Senior VLSI ASIC Logic Design Engineer

HPE Juniper Networks Multiple locations

FPGA ASIC

2d

Senior VLSI ASIC Logic Design Engineer

HPE Juniper Networks Multiple locations

FPGA ASIC

2d

Senior DRAM RTL design engineer

Micron Hyderabad, Telangana

ASIC RTL

2d

PRINCIPAL ENGINEER, ASIC DESIGN

Micron Hyderabad, Telangana

Verilog System Verilog

2d

PRINCIPAL ENGINEER, ASIC DESIGN

Micron Hyderabad, Telangana

Verilog System Verilog

2d

PRINCIPAL ENGINEER, ASIC DESIGN

Micron Hyderabad, Telangana

Verilog System Verilog

2d

Senior Engineer, DPG LPDDR Verification

Micron Hyderabad, Telangana

Verilog System Verilog

2d

Senior/Principal Design Automation Engineer, Simulation

Micron Jalisco, Chiapas

STA Static Timing

2d

Senior Engineer CAD, Physical Verification

Micron Jalisco, Chiapas

Verification

2d

Senior Engineer CAD, Physical Verification

Micron Jalisco, Chiapas

Verification

2d

Senior Robotics Verification & Validation (V&V) Engineering Manager

Johnson & Johnson Boston, Massachusetts

Verification

2d

Test Development Engineer

Broadcom Singapore, Central Singapore

DFT Design for Test

2d

Test Development Engineer

Broadcom Singapore, Central Singapore

DFT Design for Test

2d

Test Development Engineer

Broadcom Singapore, Central Singapore

DFT Design for Test

2d

Test Development Engineer

Broadcom Singapore, Central Singapore

DFT Design for Test

2d

Senior Physical Design Engineer

Broadcom San Jose, California

ASIC RTL

2d

Senior Verification Engineer - HSIO Unit Level

NVIDIA Multiple locations

FPGA UVM

2d

ASIC Design Engineer, BOOT and Power Management

NVIDIA Multiple locations

RTL Digital Design

2d

Build and Release Methodology Engineer

NVIDIA Bengaluru, Karnataka

Verilog System Verilog

2d

Senior ASIC Verification Engineer - GPU

NVIDIA Santa Clara, California

SystemVerilog ASIC

2d

Formal Verification Engineer - New College Grad 2027

NVIDIA Santa Clara, California

Verilog System Verilog

2d

RFIC System Engineer

Apple San Francisco, California

RTL SOC

2d

RFIC System Engineer

Apple San Francisco, California

RTL SOC

2d

SOC Design Verification Engineer

Apple Multiple Locations

Verilog SystemVerilog

2d

SOC Design Verification Engineer

Apple Multiple Locations

Verilog SystemVerilog

2d

MAC Design Verification Engineer

Apple Multiple Locations

Verilog SystemVerilog

2d

Wireless MAC Design Verification Engineer

Apple Multiple Locations

Verilog SystemVerilog

2d

SOC Design Verification Engineer

Qualcomm San Diego, California

ASIC RTL

2d

Analog Mixed Signal/Power Management Design Engineer (Sr up to Staff)

Qualcomm San Diego, California

VHDL Verilog

2d

CPU Physical Electrical Analysis Engineer

Qualcomm Austin, Texas

STA Place and Route

2d

GPU HLM Engineer - Cork, Ireland

Qualcomm Cork, Munster

ASIC RTL

2d

Staff Engineer - Pre/Post Si validation

Qualcomm Noida, Uttar Pradesh

ASIC SOC

2d

ASICS Design Engineer, Principal

Qualcomm Hsinchu City, Taiwan

ASIC RTL

2d

GPU Compiler Engineer - Cambridge, UK

Qualcomm Cambridge, England

ASIC RTL

2d

SOC Implementation Engineer, Lead

Qualcomm Hyderabad, Telangana

FPGA RTL

2d

CPU Design - Sr Engineer

Qualcomm Bangalore, India

VHDL Verilog

2d

CPU Design - Sr Engineer

Qualcomm Bangalore, India

VHDL Verilog

2d

Lead Engineer - CAD Physical Verification

Silicon Labs Hyderabad, Telangana

SOC Verification

2d

Sr Principal Agile Product Owner – Verification PO (26-384)

Northrop Grumman Springs, Colorado

Verification

2d

Design Engineer, Digital IP

NXP Semiconductors Bangalore, India

RTL Logic Design

2d

Senior DFT Designer

NXP Semiconductors Bangalore, India

VHDL Verilog

2d

Principal Engineer-Design (SoC Integration and RTL/IP)

Microchip Technology Bangalore, India

SystemVerilog FPGA

2d

Principal Engineer - Verification

Microchip Technology Multiple locations

Verilog SystemVerilog

2d