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Sept. 11, 2026
Emulation Performance/Debug Engineer
Physical Design Engineer, Senior Lead
Senior Performance Engineer
RISCV Infra System IP DV - Sr Staff Engineer
RISCV Infra System IP DV - Sr Lead Engineer
NPU AI Processor Synthesis Engineer- Sr Lead
RTL Design(Audio)-Sr Engineer
RTL Design(Audio)-Engineer
RTL Design (DDR) - Sr Lead Engineer
Senior Design Engineer(FPGA RTL)
Technical Recruiter
Technical Program Manager, Silicon/Hardware
Physical Design CPU Methodology Engineer
Sept. 10, 2026