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FAST Labs Senior Principal II Engineer - Electrical Digital Lead

BAE Systems Merrimack, New Hampshire

VHDL FPGA

Graphics (GPU) RTL Design Engineer

Apple Austin, Texas

Verilog System Verilog

Senior Design Verification Engineer

Blue Origin Cupertino, California

SystemVerilog ASIC

Senior Test Engineer - HBR

Blue Origin Longmont, Colorado

DFT Design for Test

Principal ASIC DFT Design Engineer - Terawave

Blue Origin Multiple locations

ASIC DFT

Principal SOC Performance Analysis Engineer - Terawave

Blue Origin Multiple locations

ASIC SOC

Principal Modem SOC Design Engineer - Terawave

Blue Origin Multiple locations

Verilog System Verilog

Senior Modem SOC Design Engineer - TeraWave

Blue Origin Multiple locations

Verilog System Verilog

Senior Technical Staff Engineer-Software Design

Microchip Technology Hyderabad, Telangana

VHDL Verilog

Engineer II - Physical Design

Microchip Technology Chandler, Arizona

ASIC RTL

Principal Engineer - Verification

Microchip Technology Bangalore, India

Verilog SystemVerilog

Principal Engineer - Verification

Microchip Technology Bangalore, India

Verilog SystemVerilog

Senior Engineer II - Verification

Microchip Technology Bangalore, India

Verilog System Verilog

Principal Analog Design Engineer

Analog Devices Multiple locations

SystemVerilog Digital Design

Associate System Platforms Engineer (FPGA and Software)

Analog Devices Durham, North Carolina

FPGA Digital Design

DFT Engineer

Broadcom IND-Bangalore Electronic City - S1

RTL STA

ASIC Verification Engineer

Broadcom Pune, Maharashtra

Verilog System Verilog

Emulation Engineer

Broadcom Pune, Maharashtra

Verilog SystemVerilog

Director, Digital IP Roadmap

Silicon Labs Austin, Texas

RTL SOC

Lead Engineer – CAD Digital Verification

Silicon Labs Hyderabad, Telangana

Verilog SystemVerilog

ASIC Verification Engineering Intern

HPE Juniper Networks Roseville, California

Verilog SystemVerilog

VLSI Physical Design Lead Engineer

HPE Juniper Networks Bloomington, Minnesota

FPGA ASIC

VLSI Physical Design Engineer

HPE Juniper Networks Bloomington, Minnesota

FPGA ASIC

Senior ASIC Design Verification Engineer - Slingshot

HPE Juniper Networks Bloomington, Minnesota

SystemVerilog FPGA

Slingshot Pre-Silicon Diagnostics & Validation Engineer

HPE Juniper Networks Bloomington, Minnesota

Verilog FPGA

Principal ASIC Engineering Program Manager

HPE Juniper Networks Spring, Texas

ASIC Verification

Senior VLSI Tools and Methodology Engineer

HPE Juniper Networks Spring, Texas

Verilog System Verilog

ASIC Design Verification Engineer - Slingshot

HPE Juniper Networks Bloomington, Minnesota

SystemVerilog ASIC

FAST Lab – Senior FPGA Engineer

BAE Systems Merrimack, New Hampshire

VHDL Verilog

Physical Design Engineer

Qualcomm Austin, Texas

ASIC RTL

Physical Design Engineer

Qualcomm Santa Clara, California

ASIC RTL

FY27 Intern - Softip Engineering Co-Op - Canada (4 months)

Qualcomm Ottawa, Ontario

VHDL Verilog

FY27 Intern- Integration of a RISC-V CPU into a Cache-Coherent Emulation Platform - Sophia, 6 months

Qualcomm Bainbridge, Alpes-de-Haute-Provence, France

VHDL Verilog

Senior Hardware Engineer - SoC Architecture & Design - Qualcomm - Grenoble, France

Qualcomm Grenoble, Auvergne-Rhône-Alpes

ASIC RTL

NOC DV Sr Lead Engineer

Qualcomm Bangalore, India

Verilog System Verilog

FY27 Intern- AI-Driven Power Modeling for Evaluating Power Management Mechanisms in NoC Architectures - Guyancourt, 6 months

Qualcomm Guyancourt, Île-de-France

VHDL Verilog

Sr Staff System Modelling Engineer

Qualcomm Bangalore, India

ASIC SOC

HW IP designer - Qualcomm - Guyancourt or Sophia, France

Qualcomm Bainbridge, Alpes-de-Haute-Provence, France

Verilog ASIC

CPU Server Physical Design Engineer

Qualcomm Santa Clara, California

Logic Design Synthesis

ASIC Design Senior Staff Engineer

Qualcomm Shanghai, Shanghai

ASIC RTL

Senior PDK Physical Verification Engineer

Intel Multiple locations

Verification

GPU Logic Design Engineer

Intel Bangalore, India

SystemVerilog RTL

GPU Logic Design Engineer

Intel Multiple locations

SystemVerilog RTL

Electrical Engineer - Digital Design

CACI Rochester, New York

VHDL Verilog

Senior Principal Engineer, Physical Designer

Marvell Santa Clara, California

ASIC RTL

Principal Engineer, Architecture (USB Systems & IP)

Lattice Semiconductor Multiple locations

FPGA ASIC

Senior Staff Solution Enablement Engineer

Lattice Semiconductor Penang, Malaysia

VHDL Verilog

Senior Solution Enablement Engineer

Lattice Semiconductor Penang, Malaysia

VHDL Verilog

FPGA Prototyping & Physical AI Intern

Lattice Semiconductor Penang, Malaysia

Verilog SystemVerilog

Software Requirements & Verification Engineer - Level 4

Northrop Grumman Redondo Beach, California

Verification

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