Aug. 13, 2026

Technical Staff Engineer - Characterization

Microchip Technology Hyderabad, Telangana

VHDL Verilog

1mo

Senior Engineer I- Design

Microchip Technology Chandler, Arizona

Verilog SystemVerilog

1mo

Senior Engineer - Design

Microchip Technology Burnaby, British Columbia

VHDL Verilog

1mo

Senior Engineer-I

Microchip Technology Hyderabad, Telangana

FPGA RTL

1mo

Senior Engineer Validation

Microchip Technology Hyderabad, Telangana

FPGA RTL

1mo

Senior Engineer II - Physical Design

Microchip Technology Chennai, Tamil Nadu

FPGA Static Timing

1mo

Senior Technical Staff Engineer - Verification

Microchip Technology Bangalore, India

Verilog SystemVerilog

1mo

Senior Engineer II - Physical Design

Microchip Technology Bangalore, India

VHDL Verilog

1mo

Principal Engineer - Design

Microchip Technology Hauppauge, New York

Verilog System Verilog

1mo

Engineer 1 - Test Engineer

Microchip Technology Hyderabad, Telangana

FPGA ASIC

1mo

Senior Engineer I Design

Microchip Technology Chennai, Tamil Nadu

ASIC RTL

1mo

Principal Engineer - Design for Test

Microchip Technology Bangalore, India

DFT Design for Test

1mo

Principal Engineer - Analog Design (IP Tech Lead)

Microchip Technology Multiple locations

SOC IP Design

1mo

Technical Staff Engineer-Design

Microchip Technology Neu-Ulm, Bavaria

Verilog System Verilog

1mo

Principal Engineer - Characterization

Microchip Technology Hyderabad, Telangana

VHDL Verilog

1mo

Principal Engineer - Digital Design

Microchip Technology Colorado Springs, Colorado

VHDL Verilog

1mo

Technical Staff Engineer - Design

Microchip Technology Chandler, Arizona

Verilog System Verilog

1mo

Senior engineer-1

Microchip Technology Hyderabad, Telangana

FPGA Synthesis

1mo

Principal Engineer - Analog Design

Microchip Technology Multiple locations

VHDL Verilog

1mo

Sr Engineer I - Validation (Systems)

Microchip Technology Roseville, California

VHDL Verilog

1mo

Principal Engineer - Validation (Systems)

Microchip Technology Roseville, California

VHDL Verilog

1mo

Principal Engineer - Design

Microchip Technology Roseville, California

VHDL Verilog

1mo

Principal Engineer

Microchip Technology Multiple locations

Verilog System Verilog

1mo

Senior Technical Staff Engineer - SOC Verification

Microchip Technology Bangalore, India

SystemVerilog RTL

1mo

Technical Staff Engineer - Design (FPGA Fabric)

Microchip Technology Multiple locations

Verilog FPGA

1mo

Senior Design Engineer

Microchip Technology Chennai, Tamil Nadu

Verilog System Verilog

1mo

Design Engineer

Microchip Technology Chennai, Tamil Nadu

Verilog System Verilog

1mo

Technical Staff Engineer - Design

Microchip Technology Penang, Malaysia

Verilog System Verilog

1mo

Principal Engineer – Physical Design

Microchip Technology Penang, Malaysia

VHDL Verilog

1mo

Principal Engineer – Physical Design

Microchip Technology Penang, Malaysia

VHDL Verilog

1mo

Principal Engineer - Design

Microchip Technology Burnaby, British Columbia

VHDL Verilog

1mo

Principal Engineer -Design

Microchip Technology Saskatoon, Saskatchewan

RTL Digital Design

1mo

Aug. 12, 2026

Systems Engineer

Atom Computing Boulder, Colorado

FPGA ASIC

1mo

Senior ASIC Design Engineer

Atom Computing Boulder, Colorado

SystemVerilog FPGA

1mo

Software Engineer, Space Special Programs

Anduril Multiple locations

VHDL FPGA

1mo

Senior FPGA Prototyping Engineer

K2 Space Seattle, Washington

Verilog SystemVerilog

1mo

Senior FPGA Prototyping Engineer

K2 Space United States - Remote

Verilog SystemVerilog

1mo

ASIC Physical Design Engineer, Netlisting - New College Grad 2026

NVIDIA Multiple locations

ASIC RTL

1mo

Senior Verification Engineer

NVIDIA Bengaluru, Karnataka

Verilog System Verilog

1mo

Senior Chip Design Engineer

NVIDIA Tel Aviv, Tel Aviv District

RTL Synthesis

1mo

Senior AI Architect, Foundation Models and SoC Co-Design – Autonomous Vehicles

NVIDIA Santa Clara, California

SOC

1mo

Cell Modeling and Verification Engineer - New College Grad 2026

NVIDIA Santa Clara, California

Verilog SystemVerilog

1mo

Senior IP Design Verification Engineer - XBAR IP

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

1mo

Senior DFT - Silicon Validation Engineer

NVIDIA Santa Clara, California

RTL STA

1mo

ASIC Verification Engineer

NVIDIA Hyderabad, Telangana

Verilog System Verilog

1mo

ASIC Verification Engineer

NVIDIA Hyderabad, Telangana

Verilog System Verilog

1mo

Senior Verification Engineer - Hardware

NVIDIA Santa Clara, California

VHDL Verilog

1mo

Senior Verification Engineer

NVIDIA Bengaluru, Karnataka

Verilog System Verilog

1mo

Senior Custom SOC IP Verification Engineer

NVIDIA Shanghai, Shanghai

1mo

Senior ASIC Floorplan Design Engineer

NVIDIA Multiple Locations

1mo