July 22, 2026

Signal Processing Engineer

Neuralink Austin, Texas

VHDL Verilog

1mo

Hardware/ Software Co-Design Engineer

Neuralink Austin, Texas

SystemVerilog RTL

1mo

Electrical Engineer, Compute Architecture

Neuralink Austin, Texas

Verilog SystemVerilog

1mo

Digital IC Design Engineer Intern

Neuralink South San Francisco, California, United States

SystemVerilog FPGA

1mo

Digital IC Design Engineer

Neuralink Austin, Texas

SystemVerilog RTL

1mo

Analog IC Design and Verification Engineer

Neuralink Austin, Texas

Verilog SystemVerilog

1mo

Analog and Mixed-Signal IC Design Engineer Intern

Neuralink South San Francisco, California, United States

Verilog SystemVerilog

1mo

Physical Design Engineer

Hudson River Trading Multiple locations

FPGA ASIC

1mo

Experienced Hardware Design Engineer

Hudson River Trading Multiple locations

SystemVerilog FPGA

1mo

Design Verification (DV) Engineer

Hudson River Trading Multiple locations

SystemVerilog FPGA

1mo

Senior Staff Engineer - Systems

Samsung Semiconductor San Jose, California

FPGA ASIC

1mo

Senior Staff Engineer, Design Verification

Samsung Semiconductor San Jose, California

Verilog System Verilog

1mo

Director, Design Verification

Samsung Semiconductor San Jose, California

SystemVerilog ASIC

1mo

Sr. Staff/Staff Engineer, Digital Design

InnoPhase IoT Multiple locations

Verilog SystemVerilog

1mo

Sr. Staff/Principal Engineer, Digital Design (San Diego)

InnoPhase IoT Multiple locations

VHDL Verilog

1mo

Senior SoC STA Engineer

InnoPhase IoT San Diego, California

RTL STA

1mo

Principal Engineer, Physical Design

InnoPhase IoT San Diego, California

RTL STA

1mo

Design Verification Engineer

InnoPhase IoT Bangalore, India

FPGA SOC

1mo

SoC System Hardware Architect

Baidu USA Sunnyvale, California

SOC IP Design

1mo

SoC Memory Subsystem Architect

Baidu USA Sunnyvale, California

RTL Digital Design

1mo

Senior RTL Design Engineer

Baidu USA Sunnyvale, California

VHDL Verilog

1mo

Low Power SoC Hardware Architect

Baidu USA Sunnyvale, California

RTL SOC

1mo

Design Verification Engineer

Baidu USA Sunnyvale, California

Verilog System Verilog

1mo

CPU Digital Design Engineer

Baidu USA Sunnyvale, California

FPGA RTL

1mo

CPU Design Architect / Principal Digital Design Engineer

Baidu USA Sunnyvale, California

FPGA RTL

1mo

Senior Flight Software Engineer

K2 Space Los Angeles, California

VHDL SystemVerilog

1mo

Senior Flight Software Engineer

K2 Space Seattle, Washington

VHDL SystemVerilog

1mo

Senior FPGA Engineer

K2 Space Los Angeles, California

VHDL SystemVerilog

1mo

Senior FPGA Engineer

K2 Space Seattle, Washington

VHDL SystemVerilog

1mo

Senior DFT Engineer

K2 Space Seattle, Washington

RTL DFT

1mo

Senior DFT Engineer

K2 Space United States - Remote

RTL DFT

1mo

Senior ASIC Physical Design Engineer

K2 Space United States - Remote

ASIC RTL

1mo

Senior ASIC Physical Design Engineer

K2 Space Seattle, Washington

ASIC RTL

1mo

Senior ASIC Design Verification Engineer

K2 Space United States - Remote

SystemVerilog ASIC

1mo

Senior ASIC Design Verification Engineer

K2 Space Seattle, Washington

SystemVerilog ASIC

1mo

Principal Flight Software Engineer

K2 Space Seattle, Washington

VHDL SystemVerilog

1mo

Principal Flight Software Engineer

K2 Space Los Angeles, California

VHDL SystemVerilog

1mo

Principal ASIC Physical Design Engineer

K2 Space United States - Remote

ASIC RTL

1mo

Principal ASIC Physical Design Engineer

K2 Space Seattle, Washington

ASIC RTL

1mo

Principal ASIC Design Verification Engineer

K2 Space Seattle, Washington

SystemVerilog ASIC

1mo

Principal ASIC Design Verification Engineer

K2 Space United States - Remote

SystemVerilog ASIC

1mo

OS Platform Engineer

K2 Space Los Angeles, California

VHDL SystemVerilog

1mo