Aug. 11, 2026

AI/ML Driven ASIC Design and Implementation Automation Engineer

NXP Semiconductors San Diego, California

VHDL Verilog

1mo

Senior Digital Verification Engineer

NXP Semiconductors Glasgow, Scotland

SystemVerilog UVM

1mo

Working Student (f/m/d) Digital Design

NXP Semiconductors Munich, Bavaria

Verilog System Verilog

1mo

Principal SoC Chip Lead

NXP Semiconductors Multiple locations

RTL DFT

1mo

Principal SoC Chip Lead

NXP Semiconductors Multiple locations

RTL DFT

1mo

Junior Digital Design Engineer - MCU

NXP Semiconductors Catania, Sicily

Verilog SystemVerilog

1mo

Principal Engineer

NXP Semiconductors Chandler (Office)

Verilog System Verilog

1mo

Lead Design Verification Engineer

NXP Semiconductors Noida, Uttar Pradesh

Verilog SystemVerilog

1mo

Sr. Staff Physical Design Timing Engineer (STA)

Lightmatter Boston, Massachusetts

ASIC RTL

1mo

Sr. Staff Physical Design Timing Engineer (STA)

Lightmatter Toronto, Ontario

ASIC RTL

1mo

Sr. Staff Physical Design Timing Engineer (STA)

Lightmatter Mountain View, California

ASIC RTL

1mo

Sr. Staff Physical Design Engineer

Lightmatter Toronto, Ontario

ASIC STA

1mo

Sr. Staff Physical Design Engineer

Lightmatter Mountain View, California

ASIC STA

1mo

Sr. Staff Physical Design Engineer

Lightmatter Boston, Massachusetts

ASIC STA

1mo

Staff/Sr. Staff Design Verification Engineer

Lightmatter Toronto, Ontario

SystemVerilog UVM

1mo

Staff/Sr. Staff Design Verification

Lightmatter Boston, Massachusetts

SystemVerilog UVM

1mo

Staff/Sr. Staff Design Verification

Lightmatter Mountain View, California

SystemVerilog UVM

1mo

Principal Digital (mixed-signal) Architect

Lightmatter Multiple locations

RTL Digital Design

1mo

Principal Digital (mixed-signal) Architect

Lightmatter Toronto, Ontario

RTL Digital Design

1mo

Digital Architect

Lightmatter Toronto, Ontario

RTL Digital Design

1mo

Digital Architect

Lightmatter Multiple locations

RTL Digital Design

1mo

ASIC Design and Integration Engineer

Apple Multiple Locations

SystemVerilog ASIC

1mo

Senior Microelectronics Test Engineer

Draper Cambridge, England

Digital Design Design for Test

1mo

FPGA Design Engineer

Draper Cambridge, Massachusetts

VHDL Verilog

1mo

Senior Analog/Mixed Signal ASIC Design Engineer

Draper Cambridge, Massachusetts

Verilog System Verilog

1mo

Mixed-Signal Electronic Design Engineer 2

Draper Cambridge, Massachusetts

VHDL Verilog

1mo

Senior/Principal Hardware ASIC Validation Engineer

Draper Multiple locations

ASIC Design for Test

1mo

ASIC CAD Engineer

Draper Cambridge, Massachusetts

ASIC

1mo

Project Lead ASIC Engineer

Draper Cambridge, Massachusetts

ASIC

1mo

UVM Digital Verification Engineer

Draper Cambridge, Massachusetts

Verilog System Verilog

1mo

Senior UVM Digital Verification Engineer

Draper Cambridge, Massachusetts

Verilog System Verilog

1mo

Senior Software Verification & Validation Engineer

Draper Cambridge, Massachusetts

Verification

1mo

Senior Digital ASIC Design Engineer

Draper Cambridge, Massachusetts

VHDL Verilog

1mo

PCB Designer (Starshield)

SpaceX Hawthorne, California

FPGA Digital Design

1mo

Staff FPGA Engineer, EW

Anduril Costa Mesa, California

VHDL Verilog

1mo

Staff Digital Hardware Engineer

Anduril Costa Mesa, California

VHDL Verilog

1mo

Senior Mission Software Engineer, EW

Anduril Costa Mesa, California

VHDL Verilog

1mo

Senior Manager - Advanced Hardware Compute

Anduril Costa Mesa, California

VHDL Verilog

1mo

Senior FPGA Test Engineer, Intelligence Systems

Anduril Reston, Virginia

VHDL Verilog

1mo

Senior FPGA Engineer, Space

Anduril Costa Mesa, California

VHDL Verilog

1mo

Senior FPGA Engineer

Anduril Costa Mesa, California

VHDL Verilog

1mo

Senior Embedded Software Engineer, EW

Anduril Costa Mesa, California

VHDL Verilog

1mo

Senior Embedded Engineer, EW

Anduril Costa Mesa, California

VHDL Verilog

1mo

Senior Electrical Test Engineer, Intelligence Systems

Anduril Santa Ana, California

FPGA RTL

1mo

Senior Electrical Engineer, Manufacturing Test (Active Clearance)

Anduril Costa Mesa, California

FPGA RTL

1mo

Senior Electrical Engineer, Manufacturing Test

Anduril Costa Mesa, California

FPGA RTL

1mo

Senior Air Vehicle Systems Engineer, Hardware Verification, Integration & Validation

Anduril Costa Mesa, California

Verification

1mo

Robotics Software Engineer, Verification & Validation

Anduril Costa Mesa, California

Verification

1mo

Power-Domain Verification Lead

Axiado Hyderabad, Telangana

SystemVerilog RTL

1mo

Senior FPGA/Emulation Validation Engineer

Axiado San Jose, California

FPGA ASIC

1mo