UVM Jobs in California

Sr. ASIC Design Verification Engineer (Silicon Engineering)

SpaceX Irvine, California

ASIC RTL

1mo

Sr. ASIC Design Verification Engineer (Silicon Engineering)

SpaceX Palo Alto, California

ASIC RTL

1mo

Principal Design Verification Engineer (Silicon Engineering)

SpaceX Palo Alto, California

FPGA ASIC

1mo

Principal Design Verification Engineer (Silicon Engineering)

SpaceX Irvine, California

FPGA ASIC

1mo

Design Verification Engineer (Silicon Engineering)

SpaceX Irvine, California

SystemVerilog ASIC

1mo

Design Verification Engineer (Silicon Engineering)

SpaceX Palo Alto, California

SystemVerilog ASIC

1mo

ASIC Design Engineer - Digital DSP Design & Analog/Mixed-Signal

Celero Communications, Inc. Multiple locations

Verilog SystemVerilog

1mo

Emulation Software Engineer

Etched Cupertino, California

Verilog SystemVerilog

1mo

FPGA Engineer

Astranis San Francisco, California

Verilog SystemVerilog

1mo

Research Engineer, Chip Design RL (Reinforcement Learning)

Anthropic Multiple locations

FPGA ASIC

1mo

Sr. Engineer, SoC Design Verification

Tenstorrent Multiple locations

SystemVerilog RTL

1mo

CPU Verification Fellow, RISC-V High-Performance Processor

Tenstorrent Santa Clara, California

SystemVerilog FPGA

1mo

CPU Core Design Verification Testbench Lead

Tenstorrent Multiple locations

RTL UVM

1mo

Manager/Director of Hardware Engineering

Baya Systems Santa Clara, California

Verilog SystemVerilog

1mo

Hardware Verification Engineer

Baya Systems Santa Clara, California

Verilog SystemVerilog

1mo

Senior Staff Engineer, Design Verification

Samsung Semiconductor San Jose, California

Verilog System Verilog

1mo

Director, Design Verification

Samsung Semiconductor San Jose, California

SystemVerilog ASIC

1mo

Design Verification Engineer

Baidu USA Sunnyvale, California

Verilog System Verilog

1mo