July 22, 2026

Sr. Engineer, SoC Design Verification

Tenstorrent Multiple locations

SystemVerilog RTL

1mo

Sr. Engineer, RTL Implementation

Tenstorrent Multiple locations

VHDL Verilog

1mo

Sr. Engineer, CPU RTL Design

Tenstorrent Multiple locations

VHDL Verilog

1mo

SOC Architect - Chiplet

Tenstorrent Munich, Bavaria

SOC Verification

1mo

Signal Integrity Engineer

Tenstorrent Multiple locations

ASIC Digital Design

1mo

Senior DFT Engineer, Architecture

Tenstorrent Tokyo, Tokyo

RTL Digital Design

1mo

RISC-V CPU Microarchitecture / RTL

Tenstorrent Santa Clara, California

VHDL Verilog

1mo

Power Architect

Tenstorrent Toronto, Ontario

Verilog RTL

1mo

Physical Design Engineer - STA

Tenstorrent Multiple locations

RTL STA

1mo

Physical Design Engineer, PnR

Tenstorrent Multiple locations

RTL STA

1mo

Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)

Tenstorrent Santa Clara, California

ASIC RTL

1mo

Physical Design Engineer

Tenstorrent Multiple locations

ASIC RTL

1mo

(India) System IP Design Engineer

Tenstorrent Bengaluru, Karnataka

Verilog SystemVerilog

1mo

Full-Chip Physical Design Verification Engineer

Tenstorrent Multiple locations

RTL SOC

1mo

Fabric SOC Architect

Tenstorrent Santa Clara, California

SOC Verification

1mo

Engineering Program Manager, RISCV

Tenstorrent Austin, Texas

DFT SOC

1mo

Emulation Engineer, Automotive Robotics

Tenstorrent Munich, Bavaria

Verilog SystemVerilog

1mo

DFT Engineer, Automotive Robotics

Tenstorrent Munich, Bavaria

RTL DFT

1mo

DFT Engineer

Tenstorrent Santa Clara, California

RTL DFT

1mo

Design Verification Lead, AI Hardware

Tenstorrent Toronto, Ontario

SystemVerilog FPGA

1mo

CPU Verification Fellow, RISC-V High-Performance Processor

Tenstorrent Santa Clara, California

SystemVerilog FPGA

1mo

CPU Core Design Verification Test Generator Lead

Tenstorrent Multiple locations

Verification

1mo

CPU Core Design Verification Testbench Lead

Tenstorrent Multiple locations

RTL UVM

1mo

AI/ML Physical Design Flow Engineer

Tenstorrent Multiple locations

RTL STA

1mo

Software Verification Engineer

Baya Systems Bengaluru, Karnataka

SOC Verification

1mo

SOC-IP Architect

Baya Systems Cambridge, England

Place and Route SOC

1mo

Microarchitect and RTL Design Engineer

Baya Systems Cambridge, England

Verilog System Verilog

1mo

Microarchitect and RTL Design Engineer

Baya Systems Santa Clara, California

Verilog System Verilog

1mo

Microarchitect and RTL Design Engineer

Baya Systems Bengaluru, Karnataka

Verilog System Verilog

1mo

Manager of Field Applications Engineering, USA

Baya Systems Multiple locations

ASIC RTL

1mo

Manager/Director of Hardware Engineering

Baya Systems Santa Clara, California

Verilog SystemVerilog

1mo

Hardware Verification Engineer

Baya Systems Austin, Texas

Verilog SystemVerilog

1mo

Hardware Verification Engineer

Baya Systems Bengaluru, Karnataka

Verilog SystemVerilog

1mo

Hardware Verification Engineer

Baya Systems Cambridge, England

Verilog SystemVerilog

1mo

Hardware Verification Engineer

Baya Systems Santa Clara, California

Verilog SystemVerilog

1mo

Director of Field Applications Engineering- Europe and APAC

Baya Systems Cambridge, England

ASIC RTL

1mo

Verification Engineer

Fractile London, England

Verilog SystemVerilog

1mo

Verification Engineer

Fractile Bristol

Verilog SystemVerilog

1mo

Senior Verification Engineer

Fractile London, England

Verilog SystemVerilog

1mo

Senior Verification Engineer

Fractile Bristol

Verilog SystemVerilog

1mo

Senior System Architect

Fractile Bristol

FPGA Digital Design

1mo

Senior System Architect

Fractile London, England

FPGA Digital Design

1mo

Senior/Principal Physical Design Engineer

Fractile Bristol

ASIC RTL

1mo

Senior/Principal Physical Design Engineer

Fractile London, England

ASIC RTL

1mo

Senior Logical Design Engineer

Fractile London, England

RTL Register Transfer

1mo

Senior Logical Design Engineer

Fractile Bristol

RTL Register Transfer

1mo

Senior/Principal DFT Engineer

Fractile Bristol

ASIC RTL

1mo

Lead Physical Design Engineer

Fractile Bristol

ASIC RTL

1mo

Lead Physical Design Engineer

Fractile London, England

ASIC RTL

1mo

Software Engineer, ASIC

Neuralink South San Francisco, California, United States

ASIC Verification

1mo