Aug. 14, 2026

Principal Mixed-Signal/Analog Design Engineer - Power/ATE

Analog Devices Multiple locations

Digital Design Synthesis

1mo

Mixed Signal Design Verification Engineer

Analog Devices Wilmington, Massachusetts

SystemVerilog RTL

1mo

Staff Embedded Software Developer

Analog Devices Vancouver, British Columbia

FPGA ASIC

1mo

Staff Digital Verification Engineer

Analog Devices Singapore, Central Singapore

SystemVerilog RTL

1mo

Staff Digital IC Design Engineer

Analog Devices Singapore, Central Singapore

RTL Logic Design

1mo

Digital Verification Lead

Analog Devices Singapore, Central Singapore

SystemVerilog UVM

1mo

Digital Design Lead

Analog Devices Singapore, Central Singapore

RTL Digital Design

1mo

Staff Design Verification Engineer – SoC and eFPGA

Analog Devices San Jose, California

Verilog SystemVerilog

1mo

Senior Engineer, Digital Design (Physical)

Analog Devices Wilmington, Massachusetts

RTL STA

1mo

Staff Digital Design Engineer

Analog Devices Munich, Bavaria

RTL Digital Design

1mo

Principal Engineer, Mixed Signal Design Engineering

Analog Devices Dallas, Texas

Digital Design SOC

1mo

SoC Verification Engineer

Intel Bangalore, India

RTL UVM

1mo

Senior Physical Design Engineer - Neuromorphic Computing

Intel Multiple locations

RTL Static Timing

1mo

Senior CPU RTL Design Engineer

Intel Multiple locations

RTL Register Transfer

1mo

Sr. DSP Systems Engineer (Silicon Engineering)

SpaceX Irvine, California

FPGA ASIC

1mo

Sr. DSP Systems Engineer (Silicon Engineering)

SpaceX Palo Alto, California

FPGA ASIC

1mo

Sr. Staff Power Performance Architect

d-Matrix Multiple locations

Remote RTL Synthesis

1mo

SoC Architect

d-Matrix Multiple locations

Remote ASIC RTL

1mo

Sr. Staff Design Verification Engineer

d-Matrix Multiple locations

Remote SystemVerilog ASIC

1mo

Principal Electrical Engineer (Sign On Bonus Available)

BAE Systems Austin, Texas

VHDL FPGA

1mo

Software Verification Engineer, Networking

NVIDIA Yokneam, Israel

Verification

1mo

Software Engineer - SONiC Verification

NVIDIA Raanana, Israel

1mo

Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU

NVIDIA Multiple locations

Verilog SystemVerilog

1mo

Senior Principal FPGA Design Engineer

BAE Systems Multiple locations

VHDL Verilog

1mo

GPU RTL Design Engineer

Apple Orlando, Florida

Verilog SystemVerilog

1mo

Aug. 13, 2026

Memory Design Engineer

Allegro MicroSystems Buenos Aires, Buenos Aires

Verilog SystemVerilog

1mo

Senior Digital Design Engineer

Allegro MicroSystems Musselburgh, Scotland

RTL Digital Design

1mo

Principal Mixed Signal Design Verification, Team Lead

Allegro MicroSystems Musselburgh, Scotland

SystemVerilog UVM

1mo

Senior Principal Digital SoC Architect

Allegro MicroSystems Richardson, Texas

Verilog SystemVerilog

1mo

Lead Engineer, Development Product Engineering

Allegro MicroSystems Alabang, Muntinlupa City, Philippines

DFT Design for Test

1mo

Software Embedded Applications Engineer (R5068)

Shield AI Dallas, Texas

SystemVerilog FPGA

1mo

Staff Engineer, FPGA Design (R5347)

Shield AI Dallas, Texas

VHDL SystemVerilog

1mo

Senior Staff Engineer, Electrical (R5116)

Shield AI Seattle, Washington

FPGA Logic Design

1mo

Sr Digital Design Engineer

NXP Semiconductors Chandler (Office)

Verilog SystemVerilog

1mo

Senior Digital Verification Engineer

NXP Semiconductors Chandler (Office)

Verilog SystemVerilog

1mo

Senior Analog Mixed Signal Verification Engineer

NXP Semiconductors Chandler (Office)

Verilog SystemVerilog

1mo

Signal Integrity Engineer - Serdes, Satellites (Starlink)

SpaceX Redmond, Washington

ASIC Digital Design

1mo

Signal Integrity Engineer - Serdes, Satellites (Starlink)

SpaceX Palo Alto, California

ASIC Digital Design

1mo

Staff Design Verification Engineer

Cerebras Systems Sunnyvale, California

SystemVerilog RTL

1mo

FPGA Design Engineer

HPE Juniper Networks Singapore, Central Singapore

Verilog System Verilog

1mo

ASIC Design Engineer

HPE Juniper Networks Sunnyvale, California

Verilog System Verilog

1mo

Principal Engineer - Hardware Sustaining

HPE Juniper Networks Singapore, Central Singapore

Verilog FPGA

1mo

Principal ASIC Design Engineer

HPE Juniper Networks Sunnyvale, California

Verilog System Verilog

1mo

Principal ASIC Test Development Engineer

HPE Juniper Networks Multiple Locations

1mo

Senior ASIC Design Verification Engineer

HPE Juniper Networks Bengaluru, Karnataka

1mo

Senior ASIC verification engineer

HPE Juniper Networks Roseville, California

Verilog System Verilog

1mo

Principal Physical Design Engineer

HPE Juniper Networks Sunnyvale, California

ASIC RTL

1mo

ASIC Principal Design Engineer

HPE Juniper Networks Bengaluru, Karnataka

1mo

ASIC Verification Engineer

HPE Juniper Networks Bengaluru, Karnataka

1mo

ASIC Design Engineer

HPE Juniper Networks Bengaluru, Karnataka

1mo