Aug. 13, 2026

ASIC Design Engineer

HPE Juniper Networks Bengaluru, Karnataka

1mo

ASIC front-end verification engineer

HPE Juniper Networks Bengaluru, Karnataka

1mo

ASIC Verification Engineer

HPE Juniper Networks Bengaluru, Karnataka

1mo

ASIC Verification Engineer

HPE Juniper Networks Bengaluru, Karnataka

1mo

ASIC Design Engineer

HPE Juniper Networks Bengaluru, Karnataka

1mo

ASIC Design Engineer

HPE Juniper Networks Bengaluru, Karnataka

1mo

ASIC DV Engineer

HPE Juniper Networks Bengaluru, Karnataka

1mo

ASIC Senior Manager

HPE Juniper Networks Bengaluru, Karnataka

1mo

ASIC Design Verification (DV) Manager

HPE Juniper Networks Multiple Locations

1mo

ASIC Design Engineer

HPE Juniper Networks Bengaluru, Karnataka

1mo

Design Verification Manager

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

1mo

AIML enhanced Design/Verification Methodology Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog FPGA

1mo

Senior Design Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog FPGA

1mo

ASIC Senior Principal Engineer: Design Verification

HPE Juniper Networks Bengaluru, Karnataka

ASIC Logic Design

1mo

Principal Hardware Engineer

HPE Juniper Networks Sunnyvale, California

Verilog FPGA

1mo

ASIC Front-end Design engineer

HPE Juniper Networks Multiple locations

Verilog ASIC

1mo

ASIC Engineer Staff

HPE Juniper Networks Bengaluru, Karnataka

FPGA ASIC

1mo

ASIC front-end Design Engineer

HPE Juniper Networks Multiple locations

Verilog ASIC

1mo

ASIC Verification Engineer

HPE Juniper Networks Bengaluru, Karnataka

FPGA ASIC

1mo

Sr. ASIC Design Engineer

HPE Juniper Networks Sunnyvale, California

Verilog System Verilog

1mo

Distinguished Technologist, ASIC Design Architect

HPE Juniper Networks Multiple locations

ASIC RTL

1mo

Director, ASIC Design & Front-End Implementation

HPE Juniper Networks Roseville, California

Verilog SystemVerilog

1mo

Senior ASIC Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

1mo

ASIC Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

1mo

FPGA Engineer

Belvedere Trading Chicago, Illinois

VHDL Verilog

1mo

FPGA Engineer

Headlands Technologies Multiple locations

VHDL Verilog

1mo

Ingénieur FPGA / FPGA Engineer

Exegy Multiple locations

Remote VHDL FPGA

1mo

Senior FPGA Designer

Exegy Multiple locations

Remote VHDL Verilog

1mo

Principal Design Verification Engineer – CPU Coherent Interconnect

SiFive Multiple locations

SystemVerilog ASIC

1mo

GPU Verification Engineer - New College Grad 2026

NVIDIA Multiple locations

FPGA ASIC

1mo

Manager, DFT - Post Silicon

NVIDIA Tel Aviv, Tel Aviv District

Verilog RTL

1mo

Project Design Lead (EX)

Nexperia San Jose, California

Verilog SystemVerilog

1mo

Design Director

Nexperia Dallas, Texas

Digital Design DFT

1mo

Mixed Signal Design Verification (MSDV) Engineer

Nexperia Dallas, Texas

Verilog SystemVerilog

1mo

Principal Professional Services Consultant - SOC Transformation & XSIAM Deployment

Palo Alto Networks Sydney, New South Wales

1mo

Principal Consultant – SOC Transformation and XSIAM Deployment

Palo Alto Networks Multiple Locations

1mo

Senior ASIC Design Verification Engineer

Palo Alto Networks Santa Clara, California

SystemVerilog ASIC

1mo

Principal Consultant – SOC Transformation & XSIAM Deployment

Palo Alto Networks Burbank, United States

1mo

Senior ASIC CAD Engineer

Palo Alto Networks Headquarters, California

1mo

Senior MSIAM SOC Engineer (Unit 42)

Palo Alto Networks Charlotte, North Carolina

1mo

2027 Internship - FPGA Engineer

Virtu Financial Dublin, Leinster

Verilog SystemVerilog

1mo

2027 Shanghai FPGA Developer Summer Internship

Optiver Shanghai, Shanghai

VHDL Verilog

1mo

Sensing & Imaging FPGA Engineer

Apple Multiple Locations

Verilog System Verilog

1mo

Sensing & Imaging FPGA Engineer

Apple Multiple Locations

Verilog System Verilog

1mo

Senior DFT Engineer

Morse Micro Sydney, New South Wales

RTL Digital Design

1mo

Senior Frontend PHY IC Design Engineer (DSP focus)

Morse Micro Morse Micro HQ - Surry Hills, AUS

Verilog SystemVerilog

1mo

Senior Electronics Test Engineer II

CesiumAstro Austin, Texas

DFT Design for Test

1mo

Senior DSP/FPGA Engineer I

CesiumAstro Milton Keynes, England

VHDL FPGA

1mo

Principal Electronics Test Engineer I

CesiumAstro Austin, Texas

DFT Design for Test

1mo

Autonomy Verification Engineer

Applied Intuition Sunnyvale, California

Verification

1mo