Aug. 12, 2026

ASIC Verification Engineer

NVIDIA Santa Clara, California

Verilog System Verilog

1mo

Senior Full Chip Layout and Physical Verification CAD Engineer

NVIDIA Multiple Locations

1mo

System Verification Co-Design Engineer - Speed and Rel

NVIDIA Santa Clara, California

Verification

1mo

Senior Manager, Test, Manufacturability, Reliability and Quality

NVIDIA Santa Clara, California

Digital Design DFT

1mo

Senior ASIC Verification Engineer

NVIDIA Multiple locations

Verilog System Verilog

1mo

GPU Verification Engineer - New College Grad 2026

NVIDIA Westford, Massachusetts

1mo

Senior VLSI Library Methodology Engineer

NVIDIA Santa Clara, California

Place and Route Synthesis

1mo

Senior Software Engineer - Verification AI Infrastructure

NVIDIA Tel Hai, Israel

1mo

Senior Network Engineer, System Verification

NVIDIA Yokneam, Israel

1mo

Senior ASIC Verification Engineer - GPU

NVIDIA Santa Clara, California

1mo

Senior System Software Engineer - CPU SoC Boot Firmware

NVIDIA Santa Clara, California

1mo

Senior ASIC Verification Engineer - PMU

NVIDIA Shanghai, Shanghai

1mo

Senior System Software Engineer - CPU SoC Boot Firmware

NVIDIA Multiple Locations

1mo

System Software Engineer - GPU and SOC

NVIDIA Multiple Locations

1mo

Senior Chip Design and Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

1mo

Senior SOC Clocks RTL Design Engineer

NVIDIA Multiple Locations

1mo

SOC Clocks RTL Design Engineer

NVIDIA Multiple Locations

1mo

Senior ASIC Verification Engineer - GPU

NVIDIA Santa Clara, California

1mo

Senior ASIC Design Engineer – Clocks IP

NVIDIA Multiple locations

Verilog ASIC

1mo

ASIC Design Engineer, Clocks

NVIDIA Shanghai, Shanghai

1mo

Senior ASIC Verification Engineer

NVIDIA Durham, North Carolina

1mo

Senior Physical Design Methodology Engineer, PPA Fusion Compiler

NVIDIA Multiple locations

Place and Route SOC

1mo

Senior Circuit Silicon Correlation DFT Engineer

NVIDIA Bengaluru, Karnataka

RTL Logic Design

1mo

ASIC TOP Floorplan Design Engineer

NVIDIA Shanghai, Shanghai

Verilog System Verilog

1mo

Senior Physical Design Methodology Engineer, Innovus Flows

NVIDIA Multiple locations

RTL STA

1mo

Senior ASIC Verification Engineer - Networking Chip Design

NVIDIA Shanghai, Shanghai

Verification

1mo

Senior System Software Engineer, SoC Power and Performance - O-RAN Infrastructure

NVIDIA Santa Clara, California

1mo

System Software Engineer

NVIDIA Yokneam, Israel

ASIC DFT

1mo

Senior Front-End Power Engineer

NVIDIA Tel Aviv, Tel Aviv District

Verilog ASIC

1mo

Front-End Integration Engineer

NVIDIA Tel Aviv, Tel Aviv District

ASIC RTL

1mo

Senior FC Verification & Simulation Infrastructure Engineer

NVIDIA Yokneam, Israel

SystemVerilog RTL

1mo

Physical Design Backend Engineer

NVIDIA Tel Aviv, Tel Aviv District

STA Place and Route

1mo

ASIC Physical Design Engineer

NVIDIA Hsinchu, Hsinchu

ASIC RTL

1mo

ASIC Verification Engineer

NVIDIA Santa Clara, California

SystemVerilog ASIC

1mo

Senior ASIC Physical Design Engineer, Netlisting

NVIDIA Multiple locations

ASIC RTL

1mo

Senior DFT Engineer

NVIDIA Santa Clara, California

RTL DFT

1mo

Senior Technical Program Manager – VLSI

NVIDIA Santa Clara, California

ASIC RTL

1mo

Senior DFT Engineer

NVIDIA Santa Clara, California

DFT SOC

1mo

Senior DFT Power Methodology Engineer

NVIDIA Santa Clara, California

RTL STA

1mo

Tech Lead Ethernet Networking Verification Engineer

NVIDIA Austin, Texas

Verification

1mo

ASIC Verification Engineer

NVIDIA Bengaluru, Karnataka

Verilog System Verilog

1mo

Senior Physical Design and Timing Engineer

NVIDIA Multiple locations

ASIC RTL

1mo

Senior Physical Design Engineer

NVIDIA Westford, Massachusetts

Place and Route Synthesis

1mo

Senior SoC Subsystem and I/O Architect - LPU

NVIDIA Multiple Locations

1mo

Physical Design Engineer, Synthesis and Implementation

NVIDIA Westford, Massachusetts

RTL Place and Route

1mo

Senior SoC Design Engineer

NVIDIA Bengaluru, Karnataka

Verilog System Verilog

1mo

Senior Manager, ASIC Chip Engineering

NVIDIA Santa Clara, California

ASIC RTL

1mo

Manager, ASIC Chip - GPU

NVIDIA Santa Clara, California

ASIC RTL

1mo

Manager, Software Verification - SONiC NOS

NVIDIA Raanana, Israel

Verification

1mo

Senior Design Verification Engineer - Interconnect IP

NVIDIA Shanghai, Shanghai

Verilog SystemVerilog

1mo