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Aug. 12, 2026
Senior IP Design Verification Engineer - XBAR IP
Senior Memory Subsystem Architect
GPU Core Pipeline IP Verification Engineer
Verification Engineer - GPU Fullchip
Verification Engineer - GPU Fullchip
Verification Engineer - PCIE
IP Verification Engineer - GPU Core Pipeline
PCIe IP Verification Engineer
Verification Engineer - HWPM
Senior Manager, System Integration – Silicon Co-Design Group
ASIC Design Engineer
Senior Design Engineer - Memory Subsystem
Senior ASIC Design Engineer - XBAR IP
Senior SOC Design Engineer - Networking Group
Principal Engineer, Project Management - Chip Design
STA Engineer
Senior Chip Design Verification Engineer
Senior System Software Engineer - CPU SoC Boot Firmware
GPU Verification Engineer
Senior GPU Architect
Senior ASIC Timing Engineer
Senior ASIC Design Engineer
ASIC Design Engineer - Hardware
Senior ASIC Physical Design Engineer, Cache Coherent Interconnects
Emulation Front-End Infrastructure Engineer
Manager, Networking Firmware Verification
Senior Chip Architect
Senior ASIC Timing Engineer, DFT
Physical Design STA Engineer
Associate Staff Verification Engineer - Wireless
Director, Verification – US & Europe
Aug. 11, 2026