Aug. 8, 2026

FPGA Design DSP Lead

BAE Systems Multiple locations

VHDL Verilog

1mo

Lead Engineer - Design Verification (Low power UPF/CPF)

Silicon Labs Hyderabad, Telangana

SystemVerilog ASIC

1mo

Digital Design Engineer I

Silicon Labs Austin, Texas

Verilog SystemVerilog

1mo

Aug. 7, 2026

Power Management Design Engineer

SiFive Multiple locations

Verilog SystemVerilog

1mo

FPGA Engineer

Cerebras Systems Remote

Remote Verilog FPGA

1mo

ASIC/SOC DFT Engineer (Silicon Engineering)

SpaceX Palo Alto, California

Verilog SystemVerilog

1mo

ASIC/SOC DFT Engineer (Silicon Engineering)

SpaceX Austin, Texas

Verilog SystemVerilog

1mo

Director- R&D Technical Head

Semtech Hyderabad, Telangana

RTL DFT

1mo

Staff SoC RTL Engineer

quadric, Inc Burlingame, California

Verilog SystemVerilog

1mo

Senior SoC Design Verification Engineer

quadric, Inc Pune, Maharashtra

Verilog SystemVerilog

1mo

Staff Electrical Engineer

Ouster San Francisco, California

FPGA ASIC

1mo

Sr. Reliability/Verification Engineer

Ouster San Francisco, California

Verification

1mo

Technical Program Manager, Silicon

Anthropic Multiple locations

ASIC RTL

1mo

Aug. 6, 2026

Staff RTL Design Engineer

SiFive Hsinchu, Hsinchu

VHDL Verilog

1mo

Senior NVM Designer

Mythic AI Palo Alto, California

Verilog System Verilog

1mo

Senior Engineer – Software Design (Platform Firmware)

Silicon Labs Hyderabad, Telangana

FPGA ASIC

1mo

Aug. 5, 2026

Digital Verification Engineer

Neuralink South San Francisco, California, United States

SystemVerilog FPGA

1mo

Silicon Engineer

Anthropic Multiple locations

ASIC RTL

1mo

Staff System Validation Engineer

SiFive Hsinchu, Hsinchu

FPGA Chisel

1mo

Staff Design Verification Engineer – Cache Verification

SiFive Hsinchu, Hsinchu

SystemVerilog FPGA

1mo

Staff Design Verification Engineer – Cache Verification

SiFive Hsinchu, Hsinchu

SystemVerilog FPGA

1mo

Senior Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog RTL

1mo

Senior Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog RTL

1mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

1mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

1mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

1mo

Senior Staff RTL Design Engineer - CPU Frontend

SiFive Santa Clara, California

VHDL Verilog

1mo

Product Power Engineer

SiFive Multiple locations

FPGA ASIC

1mo

Power Model Engineer

SiFive Multiple locations

FPGA ASIC

1mo

Core Performance Architect

SiFive Multiple locations

FPGA RTL

1mo

Core Performance Architect

SiFive Multiple locations

FPGA RTL

1mo

Core Performance Architect

SiFive Multiple locations

FPGA RTL

1mo

Aug. 4, 2026

Zebu flow Engineer

SiFive Bengaluru, Karnataka

Verilog FPGA

1mo

Senior FPGA Engineer (VHDL/Verilog)

AGAD Technology Schelle, Flanders, Belgium

VHDL Verilog

1mo

ASIC Design and Integration Engineer – Silicon Security

Apple Cupertino, California

Verilog SystemVerilog

1mo

ASIC Design and Integration Engineer – Silicon Security

Apple Cupertino, California

ASIC RTL

1mo

Summer 2027 Silicon Engineering Internship/Co-op

SpaceX Flexible - Any SpaceX Site

VHDL Verilog

1mo

Sr. PCB Designer (Starlink)

SpaceX Bastrop, Texas

FPGA Digital Design

1mo

Spring 2027 Silicon Engineering Internship/Co-op

SpaceX Flexible - Any SpaceX Site

VHDL Verilog

1mo

Senior ASIC Emulation Engineer

K2 Space Seattle, Washington

SystemVerilog FPGA

1mo

Hardware Engineer (FPGA/ASIC)

Jane Street London, England

VHDL Verilog

1mo

Hardware Engineer (FPGA/ASIC)

Jane Street London, England

VHDL Verilog

1mo

Aug. 2, 2026

Intern - Design Verification Infrastructure Engineer - Platform

SiFive Multiple locations

Chisel Verification

1mo

Aug. 1, 2026

CPU Processor Performance Verification Engineer

Apple Santa Clara, California

Verilog System Verilog

1mo

CPU Processor Performance Verification Engineer

Apple Santa Clara, California

Verilog System Verilog

1mo

CPU Processor Performance Verification Engineer

Apple Santa Clara, California

Verilog System Verilog

1mo

CPU Microarchitect/RTL Engineer

Apple Austin, Texas

VHDL Verilog

1mo

CPU Microarchitect/RTL Engineer

Apple Austin, Texas

VHDL Verilog

1mo

CPU Microarchitect/RTL Engineer

Apple Austin, Texas

VHDL Verilog

1mo

RFIC Design Engineer

Apple Multiple Locations

RTL SOC

1mo