Sept. 3, 2026

Modem HW Design Engineer – AI Driven Next Gen Modem Hardware Development

Qualcomm San Diego, California

Verilog System Verilog

12d

RTL Design (Infra/NOC/SMMU/DDR/Peripherals)

Qualcomm Bangalore, India

FPGA ASIC

12d

CPU Architecture Performance Engineer, Senior to Staff Level

Qualcomm Hsinchu City, Taiwan

Verilog ASIC

12d

Firmware Development Principal Engineer

Qualcomm Multiple locations

FPGA SOC

12d

Emulation Methodology Engineer

Qualcomm San Diego, California

Verilog SystemVerilog

12d

SoC Front-End Integrator, Senior to Staff (Hsinchu, Taipei)

Qualcomm Taipei, Taipei

Verilog SystemVerilog

12d

High‑Speed IP Integration Engineer, Up to Snr Staff (USB/PCIe/UHS) (Hsinchu, Taipei)

Qualcomm Taipei, Taipei

Verilog SystemVerilog

12d

Interim Engineering Intern_2027_HW

Qualcomm Multiple locations

VHDL Verilog

12d

Senior C++ Software Engineer - Cork, Ireland

Qualcomm Cork, Munster

ASIC Logic Design

12d

Firmware Development Engineer, Sr. Staff

Qualcomm Multiple locations

FPGA SOC

12d

GPU/AI Power Performance Staff Engineer

Qualcomm Bangalore, India

Verilog ASIC

12d

CPUSS Verification (Power Management), Staff/ Senior Staff

Qualcomm Bangalore, India

SystemVerilog RTL

12d

USB-Design Verification Senior Engineer

Qualcomm Bangalore, India

SystemVerilog FPGA

12d

AI Systems Hardware Engineer

Qualcomm Multiple locations

ASIC SOC

12d

CPU Micro-Architect RTL Engineer

Qualcomm Austin, Texas

RTL SOC

12d

Baseband Hardware/Systems Engineer

Qualcomm San Diego, California

ASIC DFT

12d

GPU Design Integration Engineer

Qualcomm San Diego, California

SystemVerilog ASIC

12d

Senior Staff, DFT Engineering

Qualcomm Ho Chi Minh City, Hồ Chí Minh

Verilog System Verilog

12d

Staff Engineer – Synthesized Model IP Design

Qualcomm Bangalore, India

Verilog SystemVerilog

12d

Senior Verification Engineer / Lead Verification Engineer

Qualcomm Bangalore, India

Verilog SystemVerilog

12d

CPU Design Verification Principal Engineer

Qualcomm Bangalore, India

Verilog System Verilog

12d

CPU STA - Sr/Lead/Staff/Sr Staff Engineer

Qualcomm Hyderabad, Telangana

Verilog ASIC

12d

2026 Intern-Digital Design/Verification Engineer

Qualcomm Shanghai, Shanghai

ASIC RTL

12d

2026 Intern-Physical Design Engineer

Qualcomm Shanghai, Shanghai

Verilog Synthesis

12d

2026 Intern-Embedded SW Engineer(SOC)

Qualcomm Shanghai, Shanghai

SOC

12d

Design Engineer (Low Power)

Qualcomm Santa Clara, California

ASIC RTL

12d

Peripherals Design Verification -Sr Staff Engineer

Qualcomm Bangalore, India

Verilog System Verilog

12d

3D Memory Chip Architect and Design, Principal Engineer

Qualcomm San Diego, California

Verilog ASIC

12d

DRAM Circuit Design, Staff

Qualcomm Seoul, Seoul

ASIC RTL

12d

Camera Frontend Implementation Engineer

Qualcomm Vancouver, British Columbia

ASIC RTL

12d

Senior Computer Vision Algorithm Engineer – Hardware Co‑Optimization (Edge AI/SoC)

Qualcomm Taipei, Taipei

FPGA RTL

12d

Physical Design Engineer, Senior to Staff Level

Qualcomm Taipei, Taipei

ASIC STA

12d

Fundamental IP Design Kit and Characterization Manager

Qualcomm Hsinchu City, Taiwan

Verilog SystemVerilog

12d

Network-on-chip/interconnect Design -Staff Engineer

Qualcomm Bangalore, India

Verilog RTL

12d

Design (WLAN )

Qualcomm Bangalore, India

FPGA Logic Design

12d

GPU Implementation Engineer(Austin & San Diego)

Qualcomm Austin, Texas

Verilog System Verilog

12d

Graphics (GPU) Hardware Project Engineer

Qualcomm San Diego, California

ASIC RTL

12d

Synthesis Engineer, Sr Lead

Qualcomm Bangalore, India

RTL Synthesis

12d

RTL Design(Turing-AI/ML)-Sr Engineer/Sr Lead

Qualcomm Bangalore, India

Verilog System Verilog

12d

Camera DV Engineer

Qualcomm San Diego, California

Verilog System Verilog

12d

PMIC Design Engineer

Qualcomm Bangalore, India

Verilog System Verilog

12d

GPU (RTL) Design - Sr Lead

Qualcomm Bangalore, India

Verilog System Verilog

12d

Analog/Mixed Signal PLL Analog Designers

Qualcomm Bangalore, India

FPGA Digital Design

12d

Peripherals Design Verification -Sr Staff Engineer

Qualcomm Bangalore, India

Verilog System Verilog

12d

Physical Design Engineer

Apple Austin, Texas

RTL STA

12d

Member of Technical Staff I

Lattice Semiconductor Chennai, Tamil Nadu

FPGA SOC

12d

Member of Technical Staff I

Lattice Semiconductor Chennai, Tamil Nadu

FPGA SOC

12d

Systems Engineer III — Lunar Human Landing System (HLS)

Blue Origin Multiple locations

HLS Verification

12d

Director, ASIC Software Engineering

Blue Origin Kraków, Lesser Poland Voivodeship

FPGA ASIC

12d

ASIC Engineering Director

Blue Origin Kraków, Lesser Poland Voivodeship

Verilog SystemVerilog

12d