Aug. 13, 2026

Staff Design Verification Test Engineer

Anduril Costa Mesa, California

Verification

1mo

Physical Design Engineer, AI Accelerator IP

Tenstorrent Multiple locations

RTL STA

1mo

Senior- Scaled Inorganic Particle Synthesis Scientist

AeroVironment WPAFB

Synthesis

1mo

FPGA Engineer

AeroVironment Albuquerque, New Mexico

VHDL Verilog

1mo

ASIC/FPGA Design Engineer

Intel Penang, Malaysia

1mo

Senior Formal Verification Engineer – AI SoC Development

Intel Multiple Locations

1mo

Senior Director, AI SOC Design Verification

Intel Santa Clara, California

1mo

Mixed Signal Logic Design Engineer

Intel Penang, Malaysia

1mo

Director, SoC Design Engineering

Intel Multiple Locations

1mo

EDA Tools Hardware Engineer

Intel Multiple locations

STA Static Timing

1mo

IP RTL Design Engineer

Intel Bangalore, India

VHDL Verilog

1mo

CPU RTL Design Engineer

Intel Multiple Locations

1mo

CPU HVM Functional-Test Verification Engineer

Intel Penang, Malaysia

1mo

CPU Design Verification Engineer

Intel Penang, Malaysia

1mo

Memory Circuit Design Engineer

Intel Multiple locations

ASIC IP Design

1mo

Senior RTL Design Engineer

Intel Bangalore, India

1mo

Physical Design Engineer

Intel Guadalajara, Jalisco

RTL STA

1mo

ASIC and Custom Silicon Sales Leader

Intel Multiple Locations

1mo

Security Software Development Engineer

Intel Haifa, Haifa District

Verilog System Verilog

1mo

CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG)

Intel Multiple locations

Verilog System Verilog

1mo

Pre-si Verification Engineer

Intel Bangalore, India

1mo

CPU DFT Manager

Intel Bangalore, India

1mo

ASIC and Custom Silicon Sales Account Manager - Americas region

Intel Santa Clara, California

1mo

Graduate Talent (CPU-SoC Silicon Design)

Intel Multiple locations

RTL Register Transfer

1mo

Physical Design Engineer

Intel Guadalajara, Jalisco

RTL Static Timing

1mo

Principal Engineer - Standard Cell Design

Intel Multiple locations

SOC IP Design

1mo

Senior USB IP Design Verification Engineer

Intel Multiple locations

Verilog System Verilog

1mo

ASIC and Custom Silicon Sales Account Manager for Asia Pacific & Japan (APJ)

Intel Multiple locations

ASIC SOC

1mo

Senior Design Verification Engineer

Intel Santa Clara, California

SystemVerilog FPGA

1mo

SoC Power Management Architect

Intel Bangalore, India

SOC

1mo

Static Timing Analysis Engineer

Intel Bangalore, India

Logic Design Static Timing

1mo

SoC Logic Design Engineer

Intel Multiple locations

Verilog ASIC

1mo

DFT Implementation Engineer

Intel Austin, Texas

VHDL Verilog

1mo

Senior CPU Physical Design Engineer

Intel Austin, Texas

RTL Logic Design

1mo

CPU Circuit Design Lead

Intel Bangalore, India

Verilog Digital Design

1mo

Server CPU SoC Architect

Intel Multiple locations

SOC Verification

1mo

CPU Verification Engineer

Intel Austin, Texas

SystemVerilog RTL

1mo

CPU Circuit Design Engineer

Intel Haifa, Haifa District

RTL Synthesis

1mo

IP RTL Senior Design Engineer

Intel Bangalore, India

Verilog System Verilog

1mo

DFT Design Engineer

Intel Bangalore, India

Verilog System Verilog

1mo

SW engineer - Silicon CAD tool development

Intel Santa Clara, California

Verilog SystemVerilog

1mo

CPU Verification Engineer

Intel Multiple locations

VHDL Verilog

1mo

Senior Physical Design Engineer (CPU)

Intel Hillsboro, Oregon

RTL STA

1mo

Mid-level Physical Design Engineer CPU

Intel Hillsboro, Oregon

RTL STA

1mo

CPU Physical Design Engineer

Intel Austin, Texas

RTL Static Timing

1mo

Senior ASIC DFT Engineer

Intel Haifa, Haifa District

DFT Verification

1mo

Senior CPU Physical Design Engineer

Intel Haifa, Haifa District

RTL STA

1mo

Senior EDA Tools Software Engineer

Intel Santa Clara, California

Verilog System Verilog

1mo

Mixed Signal validation engineer

Intel Multiple locations

Verilog System Verilog

1mo

DFT Application Engineer

Intel Multiple locations

ASIC RTL

1mo