Aug. 1, 2026

FE RTL Infrastructure - CAD Engineer

Apple Multiple Locations

Verilog SystemVerilog

1mo

SoC Machine Learning Design Engineer

Apple Multiple Locations

RTL SOC

1mo

Mixed Signal RTL Design Engineer

Apple Multiple Locations

RTL Verification

1mo

RFIC - PLL Design Engineer

Apple Multiple Locations

SystemVerilog RTL

1mo

Connectivity Systems Engineer

Apple San Francisco, California

VHDL Verilog

1mo

PHY Design Verification Engineer

Apple Multiple Locations

RTL SOC

1mo

Wireless Design Verification Engineer

Apple Multiple Locations

RTL SOC

1mo

ASIC Design Engineer - Cache Controller

Apple Santa Clara, California

RTL Register Transfer

1mo

RFIC System Engineer

Apple San Francisco, California

RTL SOC

1mo

RFIC System Engineer

Apple San Francisco, California

RTL SOC

1mo

CPU Microarchitect/RTL Engineer - Fetch, Out of Order

Apple Santa Clara, California

RTL Verification

1mo

C - Focused Design Verification Engineer

Apple Multiple Locations

Verilog SystemVerilog

1mo

Staff Design Verification Engineer, AI HW

Tenstorrent Multiple locations

SystemVerilog RTL

1mo

Systems Debug Engineer- EE

Cerebras Systems Sunnyvale, California

Remote ASIC DFT

1mo

Senior HSIO Digital Design Engineer

Samsung Semiconductor San Jose, California

Digital Design SOC

1mo

2027 Internship- Hardware Engineer (FPGA)

Virtu Financial Austin, Texas

Verilog SystemVerilog

1mo

July 31, 2026

Principal DFT Engineer (Silicon Engineering)

SpaceX Irvine, California

Verilog SystemVerilog

1mo

Principal DFT Engineer (Silicon Engineering)

SpaceX Austin, Texas

Verilog SystemVerilog

1mo

Principal DFT Engineer (Silicon Engineering)

SpaceX Palo Alto, California

Verilog SystemVerilog

1mo

Sr./Staff /Sr. Staff Engineer, IP Design (ASIC)

SK hynix memory solutions America Inc. San Jose, California

Verilog SystemVerilog

1mo

ASIC Design Engineer

SK hynix memory solutions America Inc. San Jose, California

Verilog SystemVerilog

1mo

Principal Design Validation & Test (DVT) Engineer

Celero Communications, Inc. Irvine, California

ASIC RTL

1mo

July 30, 2026

System Emulation and Evaluation Engineer

Cirrus Logic Edinburgh, Scotland

FPGA ASIC

1mo

System Emulation and Evaluation Engineer

Cirrus Logic Newbury, England

FPGA ASIC

1mo

Staff Digital Design Engineer

Cirrus Logic Austin, Texas

Verilog ASIC

1mo

Staff Design Verification Engineer

Cirrus Logic Austin, Texas

VHDL Verilog

1mo

Staff Analog Design Engineer

Cirrus Logic Austin, Texas

Verilog SystemVerilog

1mo

Senior Staff Post Silicon Validation Engineer - Global Operations

Cirrus Logic Austin, Texas

FPGA Digital Design

1mo

Senior Staff Digital Design Engineer

Cirrus Logic Austin, Texas

Verilog ASIC

1mo

Senior Staff Design Verification Engineer

Cirrus Logic Austin, Texas

VHDL Verilog

1mo

Senior Staff Analog Design Engineer

Cirrus Logic Austin, Texas

Verilog SystemVerilog

1mo

Senior Physical Design Engineer

Cirrus Logic Edinburgh, Scotland

ASIC RTL

1mo

Senior Formal Verification Engineer (CH-64001149)

Cirrus Logic Austin, Texas

Verilog System Verilog

1mo

Senior Digital Design Engineer (#OAEG3)

Cirrus Logic Edinburgh, Scotland

Verilog SystemVerilog

1mo

Senior Digital Design Engineer

Cirrus Logic Austin, Texas

Verilog ASIC

1mo

Senior DFT Engineer

Cirrus Logic Edinburgh, Scotland

Verilog SystemVerilog

1mo

Senior Design Verification Engineer (BO - 01)

Cirrus Logic Chandler, Arizona

VHDL Verilog

1mo

Senior Design Verification Engineer

Cirrus Logic Austin, Texas

VHDL Verilog

1mo

Senior Analog Design Engineer

Cirrus Logic Austin, Texas

Verilog SystemVerilog

1mo

Principal SoC Architect (ML Accelerators)

Cirrus Logic Austin, Texas

FPGA ASIC

1mo

Physical Design Engineer (AS-64000921)

Cirrus Logic Austin, Texas

ASIC RTL

1mo

NVM Circuit Design Engineer (MH-US-50021294)

Cirrus Logic Austin, Texas

DFT Design for Test

1mo

NVM Circuit Design Engineer (MH-UK-50021294)

Cirrus Logic Edinburgh, Scotland

DFT Design for Test

1mo

Mixed Signal Modelling and Verification Engineer (#GNEG4)

Cirrus Logic Edinburgh, Scotland

Verilog SystemVerilog

1mo

Embedded Software Engineer (NWB)

Cirrus Logic Newbury, England

FPGA ASIC

1mo

Embedded Software Engineer (LDN)

Cirrus Logic London, England

FPGA ASIC

1mo

Director, Engineering IT Operations

Cirrus Logic Austin, Texas

RTL Place and Route

1mo

Director, Engineering IT Operations

Cirrus Logic Edinburgh, Scotland

RTL Place and Route

1mo

Digital Design Engineer (TR-NWB)

Cirrus Logic Newbury, England

Verilog SystemVerilog

1mo

Digital Design Engineer (AP)

Cirrus Logic Edinburgh, Scotland

Verilog SystemVerilog

1mo