July 28, 2026

Senior DFT Engineer

Omni Design Technologies Bangalore, Indiana

VHDL Verilog

1mo

Sales Director, Semiconductor Mixed Signal IP and ASIC, Various Locations (US-California, Europe, Taiwan, Japan, Korea)

Omni Design Technologies Milpitas, California

ASIC SOC

1mo

Principal / Lead Wireless Communications System Architect

Omni Design Technologies Milpitas, California

RTL SOC

1mo

Principal / Lead DSP & Systems Architect — Ultra High-Speed SerDes

Omni Design Technologies Milpitas, California

RTL SOC

1mo

Physical Design Lead/Manager

Omni Design Technologies Hyderabad, Indiana

RTL Synthesis

1mo

EDA CAD Engineer - Mixed Signal IC Design

Omni Design Technologies Hyderabad, Telangana

Digital Design SOC

1mo

Digital/RTL IC Design Engineer

Omni Design Technologies Bangalore, Indiana

Verilog SystemVerilog

1mo

Digital Design Lead/Manager

Omni Design Technologies Hyderabad, Indiana

Verilog System Verilog

1mo

Analog/Mixed-Signal IC Verification Engineer

Omni Design Technologies Milpitas, California

Verilog Verification

1mo

SoC/ASIC Design Verification Engineer

zeroRISC Boston, Massachusetts

SystemVerilog ASIC

1mo

Senior RTL Design Engineer - CPU

SiFive Cambridge, England

VHDL Verilog

1mo

Senior RTL Design Engineer - CPU Frontend

SiFive Santa Clara, California

VHDL Verilog

1mo

Product Power Engineer

SiFive Multiple locations

FPGA ASIC

1mo

Power Infrastructure Lead

SiFive Multiple locations

FPGA ASIC

1mo

Senior Design Verification Engineer

SiFive Hsinchu, Hsinchu

SystemVerilog FPGA

1mo

Design Verification Infrastructure Engineer - Software

SiFive Hsinchu, Hsinchu

Chisel Verification

1mo

Sr. Design Verification Infrastructure Engineer - Build

SiFive Bengaluru, Karnataka

Verification

1mo

Staff RTL Design Engineer - CPU Midcore

SiFive Cambridge, England

VHDL Verilog

1mo

Workload / Performance Model Lead

SiFive Multiple locations

FPGA RTL

1mo

SOC Architect

SiFive Multiple locations

SOC Verification

1mo

Core Performance Architect

SiFive Multiple locations

FPGA RTL

1mo

CPU Power-Management Design Engineer

SiFive Multiple locations

Verilog SystemVerilog

1mo

System Validation Engineer to Staff Engineer

SiFive Hsinchu, Hsinchu

FPGA Chisel

1mo

Principal Design Verification Engineer – High Performance CPU Subsystem

SiFive Multiple locations

RTL SOC

1mo

Senior Staff Engineer, Physical Design - NoC

SiFive Bengaluru, Karnataka

RTL Logic Design

1mo

Staff Design Verification Engineer – Coherent Interconnect

SiFive Multiple locations

SystemVerilog FPGA

1mo

Intern - Design Verification Infrastructure Engineer - Platform

SiFive Multiple locations

Chisel Verification

1mo

Staff Design Verification Infrastructure Engineer - VIPs and Testbench

SiFive Bengaluru, Karnataka

Verilog System Verilog

1mo

Staff Design Verification Infrastructure Engineer - VIPs and Testbench

SiFive Bengaluru, Karnataka

Verilog System Verilog

1mo

Staff Design Verification Engineer

SiFive Hsinchu, Hsinchu

Verification

1mo

Lead Debug/Trace/Profiling Design Engineer

SiFive Multiple locations

VHDL Verilog

1mo

Debug/Trace/Profiling Design Engineer

SiFive Multiple locations

VHDL Verilog

1mo

Staff Engineer

SiFive Ahmedabad, Gujarat

SystemVerilog FPGA

1mo

Interconnect Design Engineer

SiFive Multiple locations

VHDL Verilog

1mo

Staff Engineer - DV

SiFive Bengaluru, Karnataka

Verilog System Verilog

1mo

Engineer / Staff / Sr. Staff Engineer - CPU Verification (RAS)

SiFive Hyderabad, Telangana

Verilog System Verilog

1mo

Staff RTL Design Engineer - CPU LS/PF/MMU

SiFive Multiple locations

VHDL Verilog

1mo

Staff Engineer - Design Verification

SiFive Hyderabad, Telangana

SystemVerilog UVM

1mo

Senior Staff Verification Engineer For Worldguard

SiFive Bengaluru, Karnataka

Verilog SystemVerilog

1mo

Senior IP Verification Engineer(IOMMU-N)

SiFive Bengaluru, Karnataka

Verilog System Verilog

1mo

Senior Staff Design Verification Engineer – Coherent Interconnect

SiFive Multiple locations

SystemVerilog FPGA

1mo

Senior Staff Design Verification Engineer – Coherent Interconnect

SiFive Multiple locations

SystemVerilog FPGA

1mo

Principal Interconnect Design Engineer

SiFive Multiple locations

VHDL Verilog

1mo

Staff / Sr. Staff Engineer DV

SiFive Bengaluru, Karnataka

RTL UVM

1mo

Senior / Staff Design Verification Engineer

SiFive Ahmedabad, Gujarat

Verilog SystemVerilog

1mo

Staff Engineer, Physical Design

SiFive Bengaluru, Karnataka

RTL Logic Design

1mo

Platform Technologies Language & Frontend Design Engineer

SiFive Multiple locations

Chisel SOC

1mo

CPU Design Verification Engineer

SiFive Hyderabad, Telangana

Verilog System Verilog

1mo

Senior Design Verification Infrastructure Engineer - VIPs and Testbench

SiFive Bengaluru, Karnataka

Verilog System Verilog

1mo

Design Verification Engineer to Staff Engineer (Unit Level Test)

SiFive Hsinchu, Hsinchu

Verilog SystemVerilog

1mo