July 22, 2026

EDA Engineer (RFIC Engineering)

SpaceX Redmond, Washington

Digital Design STA

1mo

Design Verification Engineer (Silicon Engineering)

SpaceX Redmond, Washington

SystemVerilog ASIC

1mo

Design Verification Engineer (Silicon Engineering)

SpaceX Irvine, California

SystemVerilog ASIC

1mo

Design Verification Engineer (Silicon Engineering)

SpaceX Palo Alto, California

SystemVerilog ASIC

1mo

Design Verification Engineer (Silicon Engineering)

SpaceX Austin, Texas

SystemVerilog ASIC

1mo

Antenna Engineer (Starship)

SpaceX Hawthorne, California

FPGA HLS

1mo

ASIC Design Engineer - Digital DSP Design & Analog/Mixed-Signal

Celero Communications, Inc. Multiple locations

Verilog SystemVerilog

1mo

Principal Physical Design Engineer

Celero Communications, Inc. Multiple locations

ASIC RTL

1mo

Principal Physical Verification Engineer

Celero Communications, Inc. Multiple locations

Verification

1mo

Optical DSP Design Engineer

Celero Communications, Inc. Ottawa, Ontario

VHDL Verilog

1mo

DSP - FEC Design Engineer

Celero Communications, Inc. Ottawa, Ontario

VHDL Verilog

1mo

Sr. Staff / Principal SSD Firmware Engineer - Flash Interface Layer (FIL)

SK hynix memory solutions America Inc. San Jose, California

FPGA ASIC

1mo

Digital Modem Engineer

Jump Trading Austin, United Kingdom

FPGA ASIC

1mo

Campus FPGA Engineer (Intern)

Jump Trading London, England

VHDL Verilog

1mo

Campus ASIC Engineer (Intern)

Jump Trading Bristol

VHDL Verilog

1mo

Signal Integrity and Power Integrity Designer

Fidus Systems Remote

Remote FPGA ASIC

1mo

PCB Layout Designer

Fidus Systems Kitchener, Ontario

FPGA ASIC

1mo

FPGA Designer

Fidus Systems Ottawa, Ontario

VHDL Verilog

1mo

DSP Designer

Fidus Systems Kitchener, Ontario

FPGA ASIC

1mo

Director of Business Development

Fidus Systems Multiple locations

Remote FPGA ASIC

1mo

RTL Design Engineer

Etched Cupertino, California

ASIC RTL

1mo

Power Optimization Engineer

Etched Cupertino, California

ASIC RTL

1mo

Physical Design Engineer

Etched Cupertino, California

ASIC RTL

1mo

Performance Modeling Engineer

Etched Cupertino, California

ASIC RTL

1mo

Front-End Power Engineer

Etched Cupertino, California

Verilog SystemVerilog

1mo

Front-End CAD Engineer

Etched Cupertino, California

ASIC RTL

1mo

Emulation Software Engineer

Etched Cupertino, California

Verilog SystemVerilog

1mo

ASIC Timing Engineer

Etched Cupertino, California

ASIC RTL

1mo

Senior Hardware Engineer - Micro-Architect

quadric, Inc Burlingame, California

Verilog SystemVerilog

1mo

FPGA Engineer

Astranis San Francisco, California

Verilog SystemVerilog

1mo

Hardware Engineer (FPGA/ASIC)

Jane Street New York City, New York

VHDL Verilog

1mo

Cybersecurity Engineer - Security Operations Center (SOC)

Jane Street New York City, New York

1mo

Cybersecurity Engineer - Security Operations Center (SOC)

Jane Street New York City, New York

1mo

ASIC Physical Design Engineer

Jane Street New York City, New York

ASIC RTL

1mo

ASIC Physical Design Engineer

Jane Street London, England

ASIC RTL

1mo

ASIC Engineer

Jane Street New York City, New York

FPGA ASIC

1mo

ASIC Engineer

Jane Street London, England

FPGA ASIC

1mo

Research Engineer, Chip Design RL (Reinforcement Learning)

Anthropic Multiple locations

FPGA ASIC

1mo

Senior FPGA / RTL Design Engineer - Signal Processing

Silvus Technologies Los Angeles, California

FPGA ASIC

1mo

Senior FPGA / RTL Design Engineer - Signal Processing

Silvus Technologies Irvine, California

FPGA ASIC

1mo

Senior Electronics Design Engineer

Silvus Technologies Los Angeles, California

FPGA Digital Design

1mo

Principal FPGA / RTL Design Engineer - Signal Processing

Silvus Technologies Irvine, California

Verilog System Verilog

1mo

FPGA Design Engineer

Silvus Technologies Irvine, California

FPGA ASIC

1mo

FPGA Design Engineer

Silvus Technologies Los Angeles, California

FPGA ASIC

1mo

Verification Engineer

Tenstorrent Japan

Verilog System Verilog

1mo

Top Level Physical Design Engineer

Tenstorrent Multiple locations

RTL SOC

1mo

Technical Program Manager, Architecture

Tenstorrent Santa Clara, California

RTL DFT

1mo

Staff Engineer, Physical Design

Tenstorrent Multiple locations

ASIC RTL

1mo

Staff Engineer, CPU Core Verification

Tenstorrent Bengaluru, Karnataka

RTL UVM

1mo

Sr Staff Engineer, SoC RTL Design

Tenstorrent Toronto, Ontario

VHDL Verilog

1mo