FPGAjobs - Jobs for FPGA, ASIC and RTL engineers

Post a Job Get Job Alerts I want to be hired!

Featured FPGA Engineer - Come Build Really Cool Shit with Us

MicroNova Waterford, Michigan

VHDL Verilog

12d

Senior FPGA Design Engineer

Philips Haifa, Haifa District

VHDL Verilog

Sr. MSIAM SOC Engineer (Unit 42)

Palo Alto Networks Sydney, New South Wales

SOC

Manager, MSIAM SOC Engineering

Palo Alto Networks Remote - USA - CA

SOC

Senior Digital / Mixed-Signal IC Design or Verification Engineer

Broadcom USA-Mendota Heights-Northland

VHDL Verilog

Logic Designer and FPGA Team Leader

Johnson & Johnson Yokneam, Haifa District, Israel

Logic Designer and FPGA Tech Lead

Johnson & Johnson Yokneam, Haifa District, Israel

Principal Digital Design Engineer (AHT)

Northrop Grumman Northridge, California

FPGA ASIC

Senior Principal ASIC Implementation Engineer

BAE Systems Multiple locations

ASIC Static Timing

CPU Core Design Verification Manager

Tenstorrent Bengaluru, Karnataka

RTL UVM

Sept. 8, 2026

Member of Technical Staff II

Lattice Semiconductor Chennai, Tamil Nadu

FPGA SOC

Senior SoC Design Engineer

Lattice Semiconductor Shanghai, Shanghai

Verilog SystemVerilog

Senior Staff Design Engineer

Lattice Semiconductor Penang, Malaysia

VHDL Verilog

RFIC Digital Verification Sr Engineer

Qualcomm Bangalore, India

ASIC RTL

GPU DV Staff/Senior Staff Engineer

Qualcomm Hyderabad, Telangana

FPGA RTL

System FPGA Engineer

Qualcomm Multiple Locations

Verilog SystemVerilog

Network Processor IP Verification Sr Lead Engineer

Qualcomm Bangalore, India

Verilog System Verilog

Physical Design Engineer, Sr Staff - Hod Hasharon

Qualcomm Hod HaSharon, Central District

ASIC STA

CPU Physical Electrical Analysis Engineer, Santa Clara/Austin

Qualcomm Santa Clara, California

STA Place and Route

CPU Physical Design Timing Engineer

Qualcomm Santa Clara, California

ASIC RTL

Director, Yield Architecture & Engineering

Qualcomm San Diego, California

ASIC DFT

SOC Power Design Engineer

Qualcomm Tijuana, Baja California

ASIC RTL

Serdes PHY Analog Design Engineer

Qualcomm Bangalore, India

FPGA RTL

Software Engineer, Senior

Qualcomm Toronto, Ontario

Verilog SystemVerilog

Firmware Engineer – SerDes PHY (all levels)

Qualcomm Toronto, Ontario

Verilog SystemVerilog

Silicon Validation Engineer, Electrical and Optical Systems - (all levels)

Qualcomm Ottawa, Ontario

ASIC SOC

Digital Design Verification Engineer, Staff

Qualcomm Toronto, Ontario

Verilog SystemVerilog

Memory Designer

Qualcomm San Diego, California

ASIC SOC

CAD RTL/DV Infrastructure Engineer, Staff

Qualcomm Bangalore, India

Verilog SystemVerilog

AI/ML Camera Lead Engineer

Qualcomm San Diego, California

VHDL Verilog

GPU Design Verification Engineer, Staff

Qualcomm Boxborough, Massachusetts

VHDL Verilog

NoC (RTL) Design-Sr Lead/Staff/Sr Staff

Qualcomm Bangalore, India

SOC Verification

GPU Compiler Engineer - Cambridge, UK

Qualcomm Cambridge, England

ASIC Digital Design

Senior Staff Formal Verification Engineer

Qualcomm Multiple locations

SystemVerilog ASIC

Graphics ASICS Hardware Design Engineer

Qualcomm San Diego, California

Verilog SystemVerilog

System Performance Modeling Engineer

Qualcomm San Diego, California

ASIC SOC

Pre-Silicon verification engineer

Intel Leixlip, Leinster

Verilog System Verilog