Sept. 5, 2026

Senior Manager, Post-Silicon Validation Engineering

Lattice Semiconductor Pune, Maharashtra

VHDL Verilog

10d

Sr. Staff Engineer, Front-End Verification

Tenstorrent Multiple locations

SystemVerilog RTL

10d

Hardware Engineer (FPGA)

Virtu Financial Dublin, Leinster

VHDL SystemVerilog

10d

Principal Electrical Engineer

Rocket Lab Chantilly, Virginia

FPGA ASIC

10d

Principal Electrical Engineer

Rocket Lab Tucson, Arizona

FPGA ASIC

10d

Sept. 4, 2026

Senior ASIC Power and Thermal Engineer

NVIDIA Bengaluru, Karnataka

11d

HWQA Engineer

NVIDIA Bengaluru, Karnataka

FPGA ASIC

11d

ASIC Verification Engineer - Clocks

NVIDIA Bengaluru, Karnataka

Verilog System Verilog

11d

Principal Product Manager - Laptop GPU and SoC

NVIDIA Santa Clara, California

SOC

11d

Senior Technical Staff Engineer - Architect (SoC)

Microchip Technology Chandler, Arizona

11d

Technical Staff Engineer - CAD

Microchip Technology Hyderabad, Telangana

Verilog FPGA

11d

Engineer II - Validation (Systems)

Microchip Technology Burnaby, British Columbia

VHDL Verilog

11d

Engineer II-Emulation

Microchip Technology Burnaby, British Columbia

FPGA RTL

11d

ASIC Development Engineer

Microchip Technology Burnaby, British Columbia

VHDL Verilog

11d

Senior SoC Design Engineer

Microchip Technology Burnaby, British Columbia

Verilog System Verilog

11d

CAD-AES Program Manager

Microchip Technology Multiple locations

Digital Design Synthesis

11d

Chassis IP Senior Design Engineer

Intel Bangalore, India

Verilog System Verilog

11d

Neuromorphic Front-End Silicon Lead

Intel Multiple locations

Verilog SystemVerilog

11d

Lead SOC Consultant

HPE Juniper Networks Bengaluru, Karnataka

SOC

11d

Pre-Silicon Diagnostics Intern

HPE Juniper Networks Ft. Collins, Colorado, United States of America

FPGA ASIC

11d

ASIC Firmware and Diagnostic Intern

HPE Juniper Networks Bloomington, Minnesota

ASIC

11d

Senior Compute Subsystem Verification Engineer

Qualcomm Markham, Ontario

Verilog System Verilog

11d

Synthesis- Lead /Staff Engineer

Qualcomm Chennai, Tamil Nadu

RTL Synthesis

11d

Front-End Implementation Engineer (Staff) - Cork, Ireland

Qualcomm Cork, Munster

Verilog ASIC

11d

SoC Debug Engineer

Qualcomm San Diego, California

ASIC RTL

11d

Low Power Design/Methodology Engineer

Qualcomm San Diego, California

Verilog System Verilog

11d

Data Center SoC Power & Limits Architect

Qualcomm Multiple locations

ASIC SOC

11d

Senior HW Program Manager

Qualcomm Bangalore, India

RTL Synthesis

11d

ASIC Design Verification Engineer (Santa Clara, CA)

Qualcomm Santa Clara, California

Verilog SystemVerilog

11d

RISCV CPU System RTL Engineer

Qualcomm Multiple locations

VHDL Verilog

11d

CPU System and Compute Die Architect

Qualcomm Multiple locations

RTL Logic Design

11d

Power Integrity Design Engineer – PDN / EMIR - Cork, Ireland

Qualcomm Cork, Munster

ASIC RTL

11d

Yield Diagnostics Engineer, up to staff

Qualcomm Hsinchu City, Taiwan

ASIC Digital Design

11d

Lead CPU Firmware Verification and Validation Engineer/ Manager

Qualcomm Santa Clara, California

DFT Design for Test

11d

Senior SoC Performance Architect

Qualcomm Multiple locations

SOC

11d

ASIC Validation Engineer

Qualcomm Pune, Maharashtra

FPGA RTL

11d

Staff Machine Learning Engineer – Automotive Cybersecurity

Qualcomm San Diego, California

RTL SOC

11d

ASIC Design Verification Engineer, up to Sr. Staff

Qualcomm Hsinchu City, Taiwan

Verilog System Verilog

11d

Linux Platform & HLOS Stack Developer, Senior/Staff - Cork, Ireland

Qualcomm Cork, Munster

ASIC SOC

11d

Validation Engineer, Senior

Qualcomm Toronto, Ontario

ASIC SOC

11d

Manager Embedded Software Engineer 2

Northrop Grumman United States-California-San Diego

VHDL Verilog

11d

Principal FPGA/Firmware Engineer

CACI Colorado Springs, Colorado

VHDL Verilog

11d

PhD Position (f/m/d) - Memory-Centric NPU Architectures and Emerging Memory Technologies for Edge AI

NXP Semiconductors Hamburg, Hamburg

VHDL Verilog

11d

DfT Architect

NXP Semiconductors Multiple locations

RTL DFT

11d

Senior Principal Engineer, Physical Design Methodology & RTL-to-GDS Architecture

SiFive Bengaluru, Karnataka

RTL

11d

Senior Engineer, Physical Design - Interconnects

SiFive Bengaluru, Karnataka

RTL Place and Route

11d

Engineer II, Physical Design - Cores

SiFive Bengaluru, Karnataka

Verilog SystemVerilog

11d

Staff Engineer CPU DV

SiFive Hyderabad, Telangana

Verilog System Verilog

11d

Staff - Formal Verification Engineer

SiFive Bengaluru, Karnataka

VHDL Verilog

11d

Staff Design Verification

SiFive Hyderabad, Telangana

SystemVerilog ASIC

11d