Sept. 6, 2026

(Sr) Staff SOC Architect - AI Accelerators (Multiple Locations)

Qualcomm Multiple Locations

ASIC SOC

9d

CPU Physical Design Engineer, Senior to Senior Staff Level

Qualcomm Hsinchu City, Taiwan

ASIC RTL

9d

VLSI Design Engineer for Server / Data Center Products

Qualcomm Multiple locations

FPGA ASIC

9d

CPU Architect – Security and MMU Aspects - Hod HaSharon

Qualcomm Hod HaSharon, Central District

RTL SOC

9d

Sr. Engineer, Machine Learning Software Verification

Qualcomm Markham, Ontario

Verification

9d

CPU Physical Design CAD Engineer (Lead/Staff/Sr Staff)

Qualcomm Multiple locations

FPGA Digital Design

9d

Sr. FPGA Engineer II

Rocket Lab Chantilly, Virginia

VHDL FPGA

9d

Senior FPGA Engineer II

Rocket Lab Tucson, Arizona

VHDL FPGA

9d

Sept. 5, 2026

Staff Engineer, Design Verification Engineering

Analog Devices Bangalore, India

SystemVerilog RTL

10d

Staff Engineer, Design Verification Engineering

Analog Devices Bangalore, India

Verilog SystemVerilog

10d

FPGA Design Engineer Level 2

Northrop Grumman United States-Maryland-Linthicum

VHDL Verilog

10d

Engineer/Principal Engineer Digital-RF Subsystems I&T

Northrop Grumman Baltimore, Maryland

VHDL Verilog

10d

Principal Engineer/Sr. Principal Engineer Digital-RF Subsystems I&T Lead

Northrop Grumman Baltimore, Maryland

VHDL Verilog

10d

R10230854 Principal/ Senior Principal Hardware/Firmware CAM

Northrop Grumman Woodland Hills, California

VHDL Verilog

10d

DMA designer, up to Staff

Qualcomm Taipei, Taipei

SystemVerilog ASIC

10d

Modem Hardware Design Verification Engineer – AI Driven Next Gen Modem Hardware Development, Staff

Qualcomm Boxborough, Massachusetts

VHDL Verilog

10d

DDR STA/Timing Engineer (Staff/ Senior Staff)

Qualcomm Bangalore, India

FPGA ASIC

10d

GPU Design Engineer

Qualcomm Austin, Texas

Verilog SystemVerilog

10d

NPU/AI Processor Synthesis Sr Staff Engineer

Qualcomm Bangalore, India

ASIC RTL

10d

ASIC 3D DRAM Architect

Qualcomm Seoul, Seoul

Verilog ASIC

10d

Mixed Signal Design Verification Engineer

Qualcomm San Diego, California

SystemVerilog ASIC

10d

CPU Micro-architect/RTL Designer

Qualcomm Multiple locations

VHDL Verilog

10d

FY27 Intern - Engineering Internship 2027 - 6 months, Cork

Qualcomm Cork, Munster

VHDL Verilog

10d

Next-Gen, High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm San Diego, California

ASIC RTL

10d

Serdes PHY Analog Design Engineer

Qualcomm Bangalore, India

FPGA RTL

10d

Camera IP Verification - Sr Engineer

Qualcomm Bangalore, India

SystemVerilog FPGA

10d

SOC Design Verification Engineer-Staff

Qualcomm San Diego, California

ASIC RTL

10d

Display Synthesis Engineer, Sr Lead

Qualcomm Bangalore, India

RTL STA

10d

CPU Post Silicon Power and Performance Engineer, Senior/Staff - Cork, Ireland

Qualcomm Cork, Munster

ASIC SOC

10d

CPU Micro-architect/RTL Designer (Multiple Locations)

Qualcomm Multiple locations

VHDL Verilog

10d

Physical Design Engineer

Marvell Córdoba, Córdoba

ASIC RTL

10d

Design for Test Intern, BS - Summer 2027

Marvell Multiple locations

UVM DFT

10d

Functional Validation Intern, BS - Summer 2027

Marvell Multiple locations

FPGA ASIC

10d

Design Verification Intern, BS - Summer 2027

Marvell Multiple locations

VHDL ASIC

10d

Design Verification Intern, MS - Summer 2027

Marvell Multiple locations

VHDL ASIC

10d

Physical Design Engineer Intern, BS - Summer 2027

Marvell Multiple locations

ASIC RTL

10d

Physical Design Engineer Intern, MS - Summer 2027

Marvell Multiple locations

ASIC RTL

10d

Digital Design Engineer

Silicon Labs Oslo

VHDL Verilog

10d

Senior System Integration and Validation Engineer

NVIDIA Bengaluru, Karnataka

Logic Design DFT

10d

Senior Networking ASIC Functional Characterization Engineer

NVIDIA Yokneam, Israel

ASIC

10d

Senior ASIC Engineer, Switch SoC

NVIDIA Bengaluru, Karnataka

Verilog ASIC

10d

ASIC Design and Verification Intern, SOC - 2027

NVIDIA Shanghai, Shanghai

Verilog SystemVerilog

10d

SOC Design Team Methodology Intern - 2027

NVIDIA Shanghai, Shanghai

ASIC SOC

10d

Intel NPU Internship

Intel Leixlip, Leinster

FPGA RTL

10d

Firmware Engineer for Phased Array Communication Ground Systems

AeroVironment Albuquerque, New Mexico

FPGA ASIC

10d

Staff Design Engineer - SoC & RTL

Lattice Semiconductor Pune, Maharashtra

Verilog System Verilog

10d

Sr Design Verification Eng

Lattice Semiconductor Pune, Maharashtra

Verilog System Verilog

10d

Senior Engineer, Post Silicon Validation

Lattice Semiconductor Pune, Maharashtra

VHDL Verilog

10d

Silicon Validation Engineer

Lattice Semiconductor Pune, Maharashtra

VHDL Verilog

10d

Staff Engineer - Post Siiicon Validation

Lattice Semiconductor Pune, Maharashtra

VHDL Verilog

10d