Aug. 26, 2026

Principal Digital Design Engineer

Analog Devices Bari, Apulia

Verilog System Verilog

20d

Principal FPGA Digital Design Engineer - Signing Bonus

BAE Systems Nashua, New Hampshire

VHDL Verilog

20d

Sr. Staff Engineer - Digital Design Verification

Ambiq Micro, Inc. Austin, Texas

Verilog SystemVerilog

20d

Senior Systems Verification & Certification Engineer

ALTEN Technology USA Burlington, Vermont

Verification

20d

Aug. 25, 2026

Digital Design Engineer Intern

Analog Devices Multiple locations

VHDL Verilog

21d

Physical Design Engineer

Intel Bangalore, India

ASIC RTL

21d

Senior SRAM Engineer

NVIDIA Santa Clara, California

Verilog Static Timing

21d

Senior Design Verification Engineer - PCIE

NVIDIA Multiple locations

SystemVerilog ASIC

21d

ASIC Physical Design Engineer (RDSS Intern)

NVIDIA Hsinchu, Hsinchu

ASIC RTL

21d

ASIC Physical Design Intern - 2027

NVIDIA Hsinchu, Hsinchu

ASIC RTL

21d

IC Verification Engineer

Broadcom San Jose, California

Verilog System Verilog

21d

Design Engineer - STA

Broadcom Fort Collins, Colorado

ASIC STA

21d

SENIOR DESIGN ENGR

NXP Semiconductors Multiple locations

Verilog SystemVerilog

21d

Principal CAD Engineer Digital Verification

NXP Semiconductors Noida, Uttar Pradesh

Verilog System Verilog

21d

Principal ASIC Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

21d

Technical Staff Engineer - Design

Microchip Technology Bangalore, India

Verilog System Verilog

21d

Principal Electrical Engineer

BAE Systems Hudson, New Hampshire

VHDL Verilog

21d

Systems Architecture, Integration, and Test Engineer (Test & Verification)

Saronic Austin, Texas

Verification

21d

Senior Electrical Engineer – PCBA Schematic & Layout

Saronic Austin, Texas

FPGA DFT

21d

Senior Staff Digital Design Engineer - Audio DSP Algorithm

Syntiant Bengaluru, Karnataka

Verilog System Verilog

21d

AMS Verification Engineer (RFIC Engineering)

SpaceX Redmond, Washington

Verilog System Verilog

21d

AMS Verification Engineer (RFIC Engineering)

SpaceX Irvine, California

Verilog System Verilog

21d

Manufacturing Engineer - Data Center Hardware

Anthropic Remote-Friendly, United States

DFT Design for Test

21d

Aug. 24, 2026

Senior Digital Design - MCU

NXP Semiconductors Catania, Sicily

Verilog SystemVerilog

22d

Senior Firmware PHY Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

Verification

22d

Chip Design Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

RTL Logic Design

22d

Aug. 23, 2026

ASIC Design Engineer - Digital DSP Design & Analog/Mixed-Signal

Celero Communications, Inc. Ottawa, Ontario

Verilog SystemVerilog

23d

ASIC Design Engineer - Digital DSP Design & Analog/Mixed-Signal

Celero Communications, Inc. Irvine, California

Verilog SystemVerilog

23d

Aug. 22, 2026

Senior Engineer I - Verification

Microchip Technology Chennai, Tamil Nadu

Verilog System Verilog

24d

Principal Engineer -Technical Information

Microchip Technology Hyderabad, Telangana

FPGA RTL

24d

Avionics Engineer II - Inverter Development

Blue Origin Greater Seattle Area

FPGA Design for Test

24d

Electrical Test Engineer III - TeraWave

Blue Origin Denver, Colorado

DFT Design for Test

24d

Associate Digital Design Engineer

Analog Devices Durham, North Carolina

Verilog SystemVerilog

24d

Principal / Senior Principal Radar Modeling Simulation Analysis Systems Engineer

Northrop Grumman United States-Maryland-Baltimore

VHDL Verilog

24d

Staff Radar Modeling Simulation Analysis Systems Engineer

Northrop Grumman United States-Maryland-Baltimore

VHDL Verilog

24d

Senior Principal Digital Engineer

Northrop Grumman United States-California-Woodland Hills

VHDL Verilog

24d

CPU Physical Design Engineer

Intel Bangalore, India

VHDL Verilog

24d

CPU Floorplan Lead

Intel Bangalore, India

ASIC Logic Design

24d

NVIDIA 2027 New College Graduate: Hardware ASIC Engineering - China

NVIDIA Shanghai, Shanghai

ASIC RTL

24d

NVIDIA 2027 New College Graduate: GPU Architecture Engineering - China

NVIDIA Multiple locations

ASIC RTL

24d

ASIC Methodology, Flow and Integration Engineer

NVIDIA Multiple locations

ASIC RTL

24d

Physical Design Power Optimization and Modeling Engineer

NVIDIA Tel Aviv, Tel Aviv District

STA Place and Route

24d

Senior Architecture Energy Modeling Engineer

NVIDIA Santa Clara, California

Verilog ASIC

24d

Architecture Energy Modeling Engineer - New College Grad 2026

NVIDIA Santa Clara, California

Verilog ASIC

24d

CPU Microarchitect/RTL Engineer - Execution, Load/Store

Apple Santa Clara, California

RTL Verification

24d

Sr. Staff SoC Power & Performance Architect

Ambiq Micro, Inc. Austin, Texas

FPGA RTL

24d

Senior Electrical Engineer I/II

Rocket Lab Pasadena, California

Verilog FPGA

24d

Senior RTL Engineer, IO Die and Interconnect IP

Samsung Semiconductor San Jose, California

Verilog SystemVerilog

24d

Aug. 21, 2026

Electrical Engineering Intern (Summer 2027)

Second Order Effects Multiple Locations

VHDL Verilog

25d

Electrical Engineering Intern (Spring 2027)

Second Order Effects Multiple Locations

VHDL Verilog

25d