Aug. 20, 2026

Verification Engineer - PCIE

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

26d

Senior System Software Engineer - SoC Power

NVIDIA Multiple locations

SOC

26d

Verification Engineer - PCIE

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

26d

Senior Verification Engineer, PCIE

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

26d

Senior ASIC Verification Engineer

NVIDIA Santa Clara, California

ASIC UVM

26d

Senior ASIC Power Management Micro Architect, Chip Design

NVIDIA Tel Aviv, Tel Aviv District

ASIC RTL

26d

Chip Design Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

Verilog System Verilog

26d

Silicon Validation Engineer

Semtech San Diego, California

VHDL Verilog

26d

Sr Staff Engineer - Analog IC

Semtech Hyderabad, Telangana

Verilog SystemVerilog

26d

Digital Signal Processing and System Validation Engineer

Broadcom San Jose, California

Verilog System Verilog

26d

Foundation IP Memory Verification Engineer

Broadcom Singapore, Central Singapore

DFT Verification

26d

Foundation IP Memory Verification Engineer

Broadcom Singapore, Central Singapore

DFT Verification

26d

Foundation IP Design Engineer

Broadcom Singapore, Central Singapore

DFT Verification

26d

Foundation IP Design Engineer

Broadcom Singapore, Central Singapore

DFT Verification

26d

Foundation IP Design Engineer

Broadcom Singapore, Central Singapore

DFT Verification

26d

IO and Mixed Signal Circuit Design Engineer

Broadcom IND-Bangalore Electronic City - S1

RTL Synthesis

26d

Senior Field Applications Engineer

Microchip Technology India - Bangalore Sales

VHDL Verilog

26d

Principal Engineer- Design (FPGA)

Microchip Technology Chandler, Arizona

Verilog SystemVerilog

26d

Module Development Engineer - RF Test

Intel Phoenix, Arizona

DFT Design for Test

26d

Senior Staff Foundation IP Engineer (Arithmetic/DSP)

Lattice Semiconductor Pune, Maharashtra

VHDL Verilog

26d

Hardware Engineering Intern

BAE Systems Manassas, Virginia

VHDL Verilog

26d

Principal Electrical Engineer (Sign On Bonus Available)

BAE Systems Austin, Texas

VHDL FPGA

26d

Staff Physical Design Engineer

Silicon Labs Hyderabad, Telangana

ASIC RTL

26d

Director AI/ML Driven ASIC Design and Implementation Automation

NXP Semiconductors Multiple locations

VHDL Verilog

26d

Principal Test Development Engineer

Analog Devices Limerick, Ireland

DFT Design for Test

26d

Associate Digital Design Engineer

Analog Devices San Jose, California

Verilog SystemVerilog

26d

ASIC Design and Integration Engineer – Silicon Security

Apple Cupertino, California

Verilog SystemVerilog

26d

Sr. PCB Designer (Starship)

SpaceX Hawthorne, California

FPGA Digital Design

26d

PCB Designer (Starship)

SpaceX Hawthorne, California

FPGA Digital Design

26d

Senior RTL Engineer, Memory Centric Computing

Samsung Semiconductor San Jose, California

Verilog System Verilog

26d

Senior Physical Design Engineer

Samsung Semiconductor San Jose, California

ASIC RTL

26d

Senior Emulation Engineer

Samsung Semiconductor San Jose, California

Verilog SystemVerilog

26d

FPGA Verification Engineer, Air Dominance and Strike

Anduril Costa Mesa, California

SystemVerilog FPGA

26d

Digital Design Engineer, Air Dominance and Strike

Anduril Costa Mesa, California

VHDL Verilog

26d

Staff Analog Design Engineer, SerDes Clocking

d-Matrix Multiple locations

Remote Verilog Synthesis

26d

Aug. 18, 2026

SoC Audio Architect, Platform Architecture

Apple Multiple Locations

SOC IP Design

28d

Senior DFT Engineer

NVIDIA Santa Clara, California

ASIC RTL

28d

Physical Design STA CAD Engineer

NVIDIA Tel Aviv, Tel Aviv District

STA Static Timing

28d

Principal Physical Verification Engineer

Celero Communications, Inc. San Jose, California

Verification

28d

Principal Physical Design Engineer

Celero Communications, Inc. San Jose, California

ASIC RTL

28d

Microelectronics Integration and Test Engineer

Draper Cambridge, Massachusetts

ASIC Design for Test

28d

Mixed Signal Design Verification Engineer

Intel Bangalore, India

Verilog System Verilog

28d

Graduate FPGA Engineer (2027 Start)

Optiver Amsterdam, North Holland

VHDL Verilog

28d

FPGA Internship (2027 Start)

Optiver Amsterdam, North Holland

VHDL Verilog

28d

Senior NVM Digital Designer

Mythic AI Palo Alto, California

Verilog SystemVerilog

28d

Senior Mixed Signal / Memory Circuit Designer

Mythic AI Palo Alto, California

Verilog System Verilog

28d

Software Engineer - FPGA-Accelerated RTL Simulation

SiFive Berkeley, California

FPGA ASIC

28d

Aug. 17, 2026

DSP Firmware Engineer

Marvell Córdoba, Córdoba

Verilog SystemVerilog

29d

Design/DSP/Verification Intern - PhD Degree

Marvell Santa Clara, California

SOC

29d

Physical Design Intern

Marvell Córdoba, Córdoba

ASIC Static Timing

29d