July 28, 2026

Embedded Software Engineer - Security

Ambiq Micro, Inc. Austin, Texas

FPGA SOC

1mo

Physical Design Engineer

Cerebras Systems Sunnyvale, California

RTL STA

1mo

Design Verification Engineer

Cerebras Systems Sunnyvale, California

SystemVerilog RTL

1mo

Senior Staff Design Verification Engineer

Cerebras Systems Sunnyvale, California

SystemVerilog RTL

1mo

Senior Engineer: Post Silicon - Bring Up

Cerebras Systems Bengaluru, Karnataka

Verilog System Verilog

1mo

ASIC Architect

Cerebras Systems Sunnyvale, California

1mo

Physical Design Engineer (Bengaluru)

Cerebras Systems Bengaluru, Karnataka

RTL STA

1mo

Lead RTL Design Engineer

Cerebras Systems Sunnyvale, California

FPGA ASIC

1mo

AI Silicon Physical Design Engineer

Cerebras Systems Sunnyvale, California

RTL STA

1mo

Sr. Staff / Principal Firmware Engineer - Flash Interface Layer (FIL)

SK hynix memory solutions America Inc. San Jose, California

FPGA ASIC

1mo

July 25, 2026

Hardware Engineer (FPGA/ASIC)

Jane Street New York City, New York

VHDL Verilog

1mo

Embedded Software Designer

Fidus Systems Multiple locations

Remote FPGA ASIC

1mo

Security Analyst (SOC)

SpaceX Hawthorne, California

SOC

1mo

July 24, 2026

Principal Engineer, SOC Integration

Samsung Semiconductor San Jose, California

ASIC Static Timing

1mo

July 23, 2026

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX Palo Alto, California

ASIC RTL

1mo

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX Austin, Texas

ASIC RTL

1mo

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX Irvine, California

ASIC RTL

1mo

Sr. SI/PI Engineer - Serdes, Satellites (Starlink)

SpaceX Palo Alto, California

FPGA ASIC

1mo

Sr. Signal Integrity Engineer - Serdes, Satellites (Starlink)

SpaceX Palo Alto, California

FPGA ASIC

1mo

Sr. RTL Design Engineer (Silicon Engineering)

SpaceX Redmond, Washington

Verilog System Verilog

1mo

Sr. RTL Design Engineer (Silicon Engineering)

SpaceX Palo Alto, California

Verilog System Verilog

1mo

Sr. RTL Design Engineer (Silicon Engineering)

SpaceX Austin, Texas

Verilog System Verilog

1mo

Sr. RTL Design Engineer (Silicon Engineering)

SpaceX Irvine, California

Verilog System Verilog

1mo

Sr. PCB Designer

SpaceX Hawthorne, California

FPGA Digital Design

1mo

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

SpaceX Sunnyvale, California

ASIC DFT

1mo

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

SpaceX Austin, Texas

ASIC DFT

1mo

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

SpaceX Irvine, California

ASIC DFT

1mo

Sr. ASIC DFT Engineer (Silicon)

SpaceX Irvine, California

ASIC DFT

1mo

Sr. ASIC DFT Engineer (Silicon)

SpaceX Palo Alto, California

ASIC DFT

1mo

Sr. ASIC DFT Engineer (Silicon)

SpaceX Austin, Texas

ASIC DFT

1mo

Sr. ASIC Design Verification Engineer (Silicon Engineering)

SpaceX Irvine, California

ASIC RTL

1mo

Sr. ASIC Design Verification Engineer (Silicon Engineering)

SpaceX Palo Alto, California

ASIC RTL

1mo

Sr. ASIC Design Verification Engineer (Silicon Engineering)

SpaceX Redmond, Washington

ASIC RTL

1mo

Sr. ASIC Design Verification Engineer (Silicon Engineering)

SpaceX Austin, Texas

ASIC RTL

1mo

Sr. ASIC Design Engineer (Starshield)

SpaceX Hawthorne, California

Verilog System Verilog

1mo

Sr. Antenna Engineer (Starship)

SpaceX Hawthorne, California

FPGA HLS

1mo

July 22, 2026

RTL Design Engineer (Silicon Engineering)

SpaceX Irvine, California

VHDL Verilog

1mo

Principal Design Verification Engineer (Silicon Engineering)

SpaceX Austin, Texas

FPGA ASIC

1mo

Principal Design Verification Engineer (Silicon Engineering)

SpaceX Palo Alto, California

FPGA ASIC

1mo

Principal Design Verification Engineer (Silicon Engineering)

SpaceX Irvine, California

FPGA ASIC

1mo

Principal Design Verification Engineer (Silicon Engineering)

SpaceX Redmond, Washington

FPGA ASIC

1mo

Principal ASIC Design Engineer (Starshield)

SpaceX Hawthorne, California

Verilog System Verilog

1mo

Physical Design Engineer II (Silicon Engineering)

SpaceX Palo Alto, California

ASIC RTL

1mo

Physical Design Engineer II (Silicon Engineering)

SpaceX Austin, Texas

ASIC RTL

1mo

Physical Design Engineer II (Silicon Engineering)

SpaceX Irvine, California

ASIC RTL

1mo

PCB Designer (Starlink)

SpaceX Bastrop, Texas

FPGA Digital Design

1mo

Manager, ASIC Design Engineering (Starshield Silicon)

SpaceX Hawthorne, California

Verilog System Verilog

1mo

Lead PCB Designer (Starshield)

SpaceX Hawthorne, California

FPGA Digital Design

1mo

FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX Redmond, Washington

VHDL Verilog

1mo

EDA Engineer (RFIC Engineering)

SpaceX Irvine, California

Digital Design STA

1mo