Sept. 2, 2026

Design Verification Eng 2(IP/SoC)

Lattice Semiconductor Multiple locations

Verilog System Verilog

13d

SoC Chip Lead

Lattice Semiconductor San Jose, California

SystemVerilog FPGA

13d

Sr. Systems Engineer — Lunar Human Landing System (HLS)

Blue Origin Multiple locations

HLS Verification

13d

Principle Manufacturing PCB DFX Engineer

Blue Origin Bay Area, CA

FPGA ASIC

13d

Transfer Stage Requirements and Verification Engineer - Lunar Permanence

Blue Origin Multiple locations

Verification

13d

Sr Comms System and Modem Engineer- Terawave

Blue Origin Bay Area, CA; Greater Seattle Area; Central Texas

FPGA ASIC

13d

Senior Digital ASIC Architect

Draper Cambridge, Massachusetts

Verilog System Verilog

13d

Senior Principal Analog Engineer -Power Management

NXP Semiconductors Hsinchu

Verilog Digital Design

13d

AI/ML driven ASIC Design and Implementation Automation Engineer

NXP Semiconductors San Diego, California

VHDL Verilog

13d

Principal Digital Verification Engineer (mfd)

NXP Semiconductors Gratkorn

VHDL Verilog

13d

Principal SoC Design Lead

NXP Semiconductors Toulouse, Occitanie

SOC

13d

DFT Design Engineer

Intel Bangalore, India

RTL DFT

13d

SoC Design Verification Engineer

Intel Bangalore, India

Verilog System Verilog

13d

Design Automation Engineer - Neuromorphic Computing

Intel Multiple locations

Verilog System Verilog

13d

Product Development/DFX Lead - Neuromorphic Computing

Intel Multiple locations

Verilog System Verilog

13d

Senior Static Timing Analysis (STA) Engineer

Intel Multiple locations

Logic Design Digital Design

13d

ASIC Design Engineer - Pixel IP ANE

Apple Sunnyvale, United States

RTL Static Timing

13d

ASIC Design Engineer - Pixel IP ANE

Apple Sunnyvale, United States

RTL Static Timing

13d

Design Verification Engineer (RDSS Intern)

NVIDIA Hsinchu, Hsinchu

SystemVerilog RTL

13d

ASIC Design Engineer (RDSS Intern)

NVIDIA Hsinchu, Hsinchu

Verilog System Verilog

13d

Physical Design, VLSI - New College Grad 2027

NVIDIA Multiple locations

RTL DFT

13d

Design Engineer - STA

Broadcom Fort Collins, Colorado

ASIC STA

13d

Senior Serdes System Design Engineer/Architect

Broadcom Multiple locations

ASIC RTL

13d

Senior Digital Design Engineer

Analog Devices Bangalore, India

RTL Digital Design

13d

Senior Manager, Digital Design Engineering

Analog Devices Shanghai, Shanghai

RTL Digital Design

13d

Staff Software Engineer/Project Lead

Northrop Grumman United States-Ohio-Cincinnati

VHDL Verilog

13d

FPGA Digital Design Engineer Level 4 (AHT)

Northrop Grumman United States-California-Northridge

VHDL Verilog

13d

Staff Engineer, DRAM

Samsung Semiconductor San Jose, California

ASIC RTL

13d

System IP RTL Design Lead

Tenstorrent Bengaluru, Karnataka

Verilog SystemVerilog

13d

ECC Design Engineering Intern

SK hynix memory solutions America Inc. San Jose, California

Verilog SystemVerilog

13d

Sr. Hardware Design Engineer/Signal Integrity/FPGA

A2e Technologies San Diego, California

FPGA SOC

13d

SR. FPGA Design Engineer w/Active Clearance

A2e Technologies San Diego, California

VHDL SystemVerilog

13d

Sr. Firmware Engineer US ONLY

A2e Technologies Reston, Virginia

VHDL SystemVerilog

13d

FPGA Design & Verification Engineer-US Only

A2e Technologies Remote

Remote SystemVerilog FPGA

13d

Staff Embedded Software Designer

Kepler Communications Toronto, California

VHDL Verilog

13d

FPGA Digital Design Engineering Intern (January 2027) (4-16 months)

Kepler Communications Toronto, California

VHDL Verilog

13d

Embedded Software Engineering Intern (January 2027) (4 months)

Kepler Communications Toronto, California

VHDL Verilog

13d

Sept. 1, 2026

DFT MBIST Staff Engineer

ICS Global Soft Remote

Remote Verilog SystemVerilog

13d

CPU Circuit Design Engineer

Intel Austin, Texas

RTL STA

14d

Lead Design Engineer, SoC Design

NXP Semiconductors Pune, Maharashtra

Digital Design Verification

14d

Senior Lead Engineer - STA

NXP Semiconductors Noida, Uttar Pradesh

STA DFT

14d

Senior/Principal verification Engineer

NXP Semiconductors Hyderabad, Telangana

SystemVerilog RTL

14d

Linux Software Engineer - System Manager

NXP Semiconductors Bucharest, Bucharest

VHDL HDL

14d

SoC Architect

NXP Semiconductors Pune, Maharashtra

RTL SOC

14d

SOC chip lead

NXP Semiconductors Pune, Maharashtra

RTL DFT

14d

Junior Digital Design Engineer - MCU

NXP Semiconductors Catania, Sicily

Verilog SystemVerilog

14d

Senior QA Automation Engineer, ASIC Simulation

NVIDIA Kyiv, Kyiv

ASIC

14d

Senior Verification Engineer, SoC

NVIDIA Multiple locations

Verilog System Verilog

14d

DPU Performance Validation Engineer

NVIDIA Tel Aviv, Tel Aviv District

FPGA ASIC

14d

Senior Chip Design Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

Verilog System Verilog

14d